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apecs_bus_io.c revision 1.9 
      1 /* $NetBSD: apecs_bus_io.c,v 1.9 2000/06/29 08:58:45 mrg Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1996 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     31 
     32 __KERNEL_RCSID(1, "$NetBSD: apecs_bus_io.c,v 1.9 2000/06/29 08:58:45 mrg Exp $");
     33 
     34 #include <sys/param.h>
     35 #include <sys/systm.h>
     36 #include <sys/malloc.h>
     37 #include <sys/syslog.h>
     38 #include <sys/device.h>
     39 
     40 #include <uvm/uvm_extern.h>
     41 
     42 #include <machine/bus.h>
     43 
     44 #include <alpha/pci/apecsreg.h>
     45 #include <alpha/pci/apecsvar.h>
     46 
     47 #define	CHIP		apecs
     48 
     49 #define	CHIP_EX_MALLOC_SAFE(v)	(((struct apecs_config *)(v))->ac_mallocsafe)
     50 #define	CHIP_IO_EXTENT(v)	(((struct apecs_config *)(v))->ac_io_ex)
     51 
     52 /* IO region 1 */
     53 #define	CHIP_IO_W1_BUS_START(v)	0x00000000UL
     54 #define	CHIP_IO_W1_BUS_END(v)	0x0003ffffUL
     55 #define	CHIP_IO_W1_SYS_START(v)	APECS_PCI_SIO
     56 #define	CHIP_IO_W1_SYS_END(v)	(APECS_PCI_SIO + (0x00040000UL << 5) - 1)
     57 
     58 /* IO region 2 */
     59 #define	CHIP_IO_W2_BUS_START(v)						\
     60     ((((struct apecs_config *)(v))->ac_haxr2 & EPIC_HAXR2_EADDR) +	\
     61       0x00040000UL)
     62 #define	CHIP_IO_W2_BUS_END(v)						\
     63     ((((struct apecs_config *)(v))->ac_haxr2 & EPIC_HAXR2_EADDR) +	\
     64       0x00ffffffUL)
     65 #define	CHIP_IO_W2_SYS_START(v)	(APECS_PCI_SIO + (0x00040000UL << 5))
     66 #define	CHIP_IO_W2_SYS_END(v)	(APECS_PCI_SIO + (0x01000000UL << 5) - 1)
     67 
     68 #include <alpha/pci/pci_swiz_bus_io_chipdep.c>
     69