apecs_pci.c revision 1.1
1 /* $NetBSD: apecs_pci.c,v 1.1 1995/06/28 01:25:30 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/device.h> 34 #include <vm/vm.h> 35 36 #include <machine/autoconf.h> 37 #include <machine/pio.h> 38 39 #include <dev/isa/isavar.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <alpha/pci/pci_chipset.h> 44 #include <alpha/pci/apecsreg.h> 45 46 void apecs_setup __P((void)); 47 pcitag_t apecs_make_tag __P((int, int, int)); 48 pcireg_t apecs_conf_read __P((pcitag_t, int)); 49 void apecs_conf_write __P((pcitag_t, int, pcireg_t)); 50 int apecs_map_mem __P((pcitag_t, int, vm_offset_t *, vm_offset_t *)); 51 int apecs_pcidma_map __P((caddr_t, vm_size_t, vm_offset_t *)); 52 void apecs_pcidma_unmap __P((caddr_t, vm_size_t, int, vm_offset_t *)); 53 54 struct pci_cs_fcns apecs_p1e_cs_fcns = { /* XXX WHAT'S DIFFERENT? */ 55 apecs_setup, 56 apecs_make_tag, 57 apecs_conf_read, 58 apecs_conf_write, 59 apecs_map_mem, 60 apecs_pcidma_map, 61 apecs_pcidma_unmap, 62 }; 63 64 struct pci_cs_fcns apecs_p2e_cs_fcns = { /* XXX WHAT'S DIFFERENT? */ 65 apecs_setup, 66 apecs_make_tag, 67 apecs_conf_read, 68 apecs_conf_write, 69 apecs_map_mem, 70 apecs_pcidma_map, 71 apecs_pcidma_unmap, 72 }; 73 74 #define REGVAL(r) (*(u_int32_t *)phystok0seg(r)) 75 76 void 77 apecs_setup() 78 { 79 80 /* 81 * Set up PCI bus mastering DMA windows on the APECS chip. 82 * 83 * What the PROM wants: 84 * a 1G direct-mapped window that maps the PCI address 85 * space from 4G -> 5G to memory addresses 0 -> 1G, 86 * set up in window two. 87 * 88 * What we want: 89 * a 1G direct-mapped window that maps the PCI address 90 * space from 0 -> 1G to memory addresses 0 -> 1G. 91 * 92 * Unless we satisfy the PROM, we can't live through a reboot. 93 * If we don't do what we want, I have to write more code. 94 95 * So: 96 * Leave window two alone, map window 1 the way I want it. 97 * 98 * XXX verify that windows don't overlap 99 * XXX be trickier 100 * XXX magic numbers 101 */ 102 103 #if 0 /* should be routine to dump regs */ 104 printf("old base1 was 0x%x\n", REGVAL(EPIC_PCI_BASE_1)); 105 printf("old mask1 was 0x%x\n", REGVAL(EPIC_PCI_MASK_1)); 106 printf("old tbase1 was 0x%x\n", REGVAL(EPIC_TBASE_1)); 107 108 printf("old base2 was 0x%x\n", REGVAL(EPIC_PCI_BASE_2)); 109 printf("old mask2 was 0x%x\n", REGVAL(EPIC_PCI_MASK_2)); 110 printf("old tbase2 was 0x%x\n", REGVAL(EPIC_TBASE_2)); 111 #endif 112 113 #if 0 /* XXX STUPID PROM; MUST LEAVE WINDOW 2 ALONE. See above */ 114 /* Turn off DMA window enables in PCI Base Reg 2. */ 115 REGVAL(EPIC_PCI_BASE_2) = 0; 116 117 /* Set up Translated Base Register 2; translate to sybBus addr 0. */ 118 REGVAL(EPIC_TBASE_2) = 0; 119 120 /* Set up PCI mask register 2; map 1G space. */ 121 REGVAL(EPIC_PCI_MASK_2) = 0x3ff00000; 122 123 /* Enable window 2; from PCI address 4G, direct mapped. */ 124 REGVAL(EPIC_PCI_BASE_2) = 0x40080000; 125 #endif /* STUPID PROM */ 126 127 /* Turn off DMA window enables in PCI Base Reg 1. */ 128 REGVAL(EPIC_PCI_BASE_1) = 0; 129 130 /* Set up Translated Base Register 1; translate to sybBus addr 0. */ 131 { /* XXX */ 132 extern struct sgmapent *sgmap; 133 REGVAL(EPIC_TBASE_1) = vtophys(sgmap) >> 1; 134 } /* XXX */ 135 136 /* Set up PCI mask register 1; map 8MB space. */ 137 REGVAL(EPIC_PCI_MASK_1) = 0x00700000; 138 139 /* Enable window 1; from PCI address 8MB, direct mapped. */ 140 REGVAL(EPIC_PCI_BASE_1) = 0x008c0000; 141 142 /* 143 * Should set up HAXR1 and HAXR2... However, the PROM again 144 * wants them where they're set to be... 145 */ 146 #if 0 147 printf("old haxr0 was 0x%x\n", REGVAL(EPIC_HAXR0)); 148 printf("old haxr1 was 0x%x\n", REGVAL(EPIC_HAXR1)); 149 printf("old haxr2 was 0x%x\n", REGVAL(EPIC_HAXR2)); 150 #endif 151 152 #if 0 /* XXX STUPID PROM */ 153 /* HAXR0 is wired zero; no op. */ 154 REGVAL(EPIC_HAXR0) = 0; 155 156 /* HAXR1: maps PCI memory space above 16M. 16M -> 2G+16M. */ 157 REGVAL(EPIC_HAXR1) = 0x80000000; 158 159 /* HAXR2: maps PCI I/O space above 256K. 256K -> 256k. */ 160 REGVAL(EPIC_HAXR2) = 0; 161 #endif 162 } 163 164 pcitag_t 165 apecs_make_tag(bus, device, function) 166 int bus, device, function; 167 { 168 pcitag_t tag; 169 170 if (bus >= 256 || device >= 32 || function >= 8) 171 panic("apecs_make_tag: bad request"); 172 173 tag = (bus << 21) | (device << 16) | (function << 13); 174 #if 0 175 printf("apecs_make_tag: bus %d, device %d, function %d -> 0x%lx\n", bus, 176 device, function, tag); 177 #endif 178 return tag; 179 } 180 181 pcireg_t 182 apecs_conf_read(tag, offset) 183 pcitag_t tag; 184 int offset; /* XXX */ 185 { 186 pcireg_t *datap, data; 187 int reg = offset >> 2; /* XXX */ 188 189 if ((tag & 0x1fe00000) != 0) { 190 panic("apecs_conf_read: bus != 0?"); 191 } 192 /* XXX FILL IN HAXR2 bits. */ 193 194 datap = (pcireg_t *) 195 phystok0seg(APECS_PCI_CONF | tag | reg << 7 | 0 << 5 | 0x3 << 3); 196 if (badaddr(datap, sizeof *datap)) 197 return ((pcireg_t)-1); 198 data = *datap; 199 #if 0 200 printf("apecs_conf_read: tag 0x%lx, reg 0x%lx -> %x @ %p\n", tag, reg, 201 data, datap); 202 #endif 203 return data; 204 } 205 206 void 207 apecs_conf_write(tag, offset, data) 208 pcitag_t tag; 209 int offset; /* XXX */ 210 pcireg_t data; 211 { 212 pcireg_t *datap; 213 int reg = offset >> 2; /* XXX */ 214 215 if ((tag & 0x1fe00000) != 0) { 216 panic("apecs_conf_read: bus != 0?"); 217 } 218 /* XXX FILL IN HAXR2 bits. */ 219 220 datap = (pcireg_t *) 221 phystok0seg(APECS_PCI_CONF | tag | reg << 7 | 0 << 5 | 0x3 << 3); 222 #if 0 223 printf("apecs_conf_write: tag 0x%lx, reg 0x%lx -> 0x%x @ %p\n", tag, 224 reg, data, datap); 225 #endif 226 *datap = data; 227 } 228 229 #ifndef APECS_PCI_PMEM_START 230 #define APECS_PCI_PMEM_START 0x00100000 /* WAY XXX */ 231 #endif 232 233 vm_offset_t apecs_pci_paddr = APECS_PCI_PMEM_START; 234 235 int 236 apecs_map_mem(tag, reg, vap, pap) 237 pcitag_t tag; 238 int reg; 239 vm_offset_t *vap, *pap; 240 { 241 pcireg_t data; 242 vm_offset_t pci_pa, sb_pa; 243 244 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) 245 panic("apecs_map_mem: bad request"); 246 247 /* 248 * "HERE WE GO AGAIN!!!" 249 * 250 * The PROM has already mapped the device for us. The PROM is 251 * our friend. We wouldn't want to make the PROM unhappy. 252 * 253 * So, we take the address that's been assigned (already) to 254 * the register, and figure out what physical and virtual addresses 255 * go with it... 256 */ 257 /* 258 * Section 6.2.5.1, `Address Maps', says that a device which wants 2^n 259 * bytes of memory will hardwire the bottom n bits of the address to 0. 260 * As recommended, we write all 1s and see what we get back. 261 */ 262 data = pci_conf_read(tag, reg); 263 264 if (data & PCI_MAP_IO) 265 panic("apecs_map_mem: attempt to memory map an I/O region"); 266 267 switch (data & PCI_MAP_MEMORY_TYPE_MASK) { 268 case PCI_MAP_MEMORY_TYPE_32BIT: 269 break; 270 case PCI_MAP_MEMORY_TYPE_32BIT_1M: 271 printf("apecs_map_mem: attempt to map restricted 32-bit region\n"); 272 return EOPNOTSUPP; 273 case PCI_MAP_MEMORY_TYPE_64BIT: 274 printf("apecs_map_mem: attempt to map 64-bit region\n"); 275 return EOPNOTSUPP; 276 default: 277 printf("apecs_map_mem: reserved mapping type\n"); 278 return EINVAL; 279 } 280 281 if (data & PCI_MAP_MEMORY_CACHABLE) { 282 /* XXX probably should impact mapping location? */ 283 printf("apecs_map_mem: memory wants to be cacheable.\n"); 284 } 285 286 /* figure out where it was mapped... */ 287 pci_pa = data & PCI_MAP_MEMORY_ADDRESS_MASK; /* PCI bus address */ 288 sb_pa = ((data & 0x7fffffc) << 5) | (2L << 32); /* sysBus address */ 289 290 /* and tell the driver. */ 291 *vap = phystok0seg(sb_pa); 292 *pap = pci_pa; 293 294 #if 0 295 printf("pci_map_mem: memory mapped at 0x%lx\n", *pap); 296 printf("pci_map_mem: virtual 0x%lx\n", *vap); 297 #endif 298 299 return 0; 300 } 301 302 int 303 apecs_pcidma_map(addr, size, mappings) 304 caddr_t addr; 305 vm_size_t size; 306 vm_offset_t *mappings; 307 { 308 vm_offset_t va; 309 long todo; 310 int i; 311 312 i = 0; 313 va = (vm_offset_t)addr; 314 todo = size; 315 316 while (todo > 0) { 317 mappings[i] = vtophys(va) | 0x40000000; 318 #if 0 319 printf("a_pd_m mapping %d: %lx -> %lx -> %lx\n", i, va, 320 vtophys(va), mappings[i]); 321 #endif 322 i++; 323 todo -= PAGE_SIZE - (va - trunc_page(va)); 324 va += PAGE_SIZE - (va - trunc_page(va)); 325 } 326 return (i); 327 } 328 329 void 330 apecs_pcidma_unmap(addr, size, nmappings, mappings) 331 caddr_t addr; 332 vm_size_t size; 333 int nmappings; 334 vm_offset_t *mappings; 335 { 336 337 /* maybe XXX if diagnostic, check that mapping happened. */ 338 printf("apecs_pcidma_unmap: nada\n"); 339 } 340
Indexes created Tue Sep 23 14:10:03 GMT 2025