cia.c revision 1.43
1 /* $NetBSD: cia.c,v 1.43 1998/06/06 01:33:44 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_eb164.h" 68 #include "opt_dec_kn20aa.h" 69 #include "opt_dec_550.h" 70 71 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 72 73 __KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.43 1998/06/06 01:33:44 thorpej Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/malloc.h> 79 #include <sys/device.h> 80 #include <vm/vm.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/isa/isareg.h> 86 #include <dev/isa/isavar.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 #ifdef DEC_KN20AA 93 #include <alpha/pci/pci_kn20aa.h> 94 #endif 95 #ifdef DEC_EB164 96 #include <alpha/pci/pci_eb164.h> 97 #endif 98 #ifdef DEC_550 99 #include <alpha/pci/pci_550.h> 100 #endif 101 102 int ciamatch __P((struct device *, struct cfdata *, void *)); 103 void ciaattach __P((struct device *, struct device *, void *)); 104 105 struct cfattach cia_ca = { 106 sizeof(struct cia_softc), ciamatch, ciaattach, 107 }; 108 109 extern struct cfdriver cia_cd; 110 111 static int ciaprint __P((void *, const char *pnp)); 112 113 /* There can be only one. */ 114 int ciafound; 115 struct cia_config cia_configuration; 116 117 /* 118 * This determines if we attempt to use BWX for PCI bus and config space 119 * access. Some systems, notably with Pyxis, don't fare so well unless 120 * BWX is used. 121 */ 122 #ifndef CIA_USE_BWX 123 #define CIA_USE_BWX 1 124 #endif 125 126 int cia_use_bwx = CIA_USE_BWX; 127 128 int 129 ciamatch(parent, match, aux) 130 struct device *parent; 131 struct cfdata *match; 132 void *aux; 133 { 134 struct mainbus_attach_args *ma = aux; 135 136 /* Make sure that we're looking for a CIA. */ 137 if (strcmp(ma->ma_name, cia_cd.cd_name) != 0) 138 return (0); 139 140 if (ciafound) 141 return (0); 142 143 return (1); 144 } 145 146 /* 147 * Set up the chipset's function pointers. 148 */ 149 void 150 cia_init(ccp, mallocsafe) 151 struct cia_config *ccp; 152 int mallocsafe; 153 { 154 155 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM); 156 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO); 157 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK; 158 159 /* 160 * Determine if we have a Pyxis. Only two systypes can 161 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX) 162 * and the DEC_550 systype (Miata). 163 */ 164 if ((hwrpb->rpb_type == ST_EB164 && 165 (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) || 166 hwrpb->rpb_type == ST_DEC_550) 167 ccp->cc_flags |= CCF_ISPYXIS; 168 169 /* 170 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register. 171 */ 172 if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0) 173 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG); 174 else 175 ccp->cc_cnfg = 0; 176 177 /* 178 * Use BWX iff: 179 * 180 * - It hasn't been disbled by the user, 181 * - it's enabled in CNFG, 182 * - we're implementation version ev5, 183 * - BWX is enabled in the CPU's capabilities mask (yes, 184 * the bit is really cleared if the capability exists...) 185 */ 186 if (cia_use_bwx != 0 && 187 (ccp->cc_cnfg & CNFG_BWEN) != 0 && 188 alpha_implver() == ALPHA_IMPLVER_EV5 && 189 alpha_amask(ALPHA_AMASK_BWX) == 0) { 190 u_int32_t ctrl; 191 192 ccp->cc_flags |= CCF_USEBWX; 193 194 /* 195 * For whatever reason, the firmware seems to enable PCI 196 * loopback mode if it also enables BWX. Make sure it's 197 * enabled if we have an old, buggy firmware rev. 198 */ 199 alpha_mb(); 200 ctrl = REGVAL(CIA_CSR_CTRL); 201 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) { 202 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 203 alpha_mb(); 204 } 205 } 206 207 if (!ccp->cc_initted) { 208 /* don't do these twice since they set up extents */ 209 if (ccp->cc_flags & CCF_USEBWX) { 210 cia_bwx_bus_io_init(&ccp->cc_iot, ccp); 211 cia_bwx_bus_mem_init(&ccp->cc_memt, ccp); 212 } else { 213 cia_swiz_bus_io_init(&ccp->cc_iot, ccp); 214 cia_swiz_bus_mem_init(&ccp->cc_memt, ccp); 215 } 216 } 217 ccp->cc_mallocsafe = mallocsafe; 218 219 cia_pci_init(&ccp->cc_pc, ccp); 220 221 ccp->cc_initted = 1; 222 } 223 224 void 225 ciaattach(parent, self, aux) 226 struct device *parent, *self; 227 void *aux; 228 { 229 struct cia_softc *sc = (struct cia_softc *)self; 230 struct cia_config *ccp; 231 struct pcibus_attach_args pba; 232 char bits[64]; 233 const char *name; 234 int pass; 235 236 /* note that we've attached the chipset; can't have 2 CIAs. */ 237 ciafound = 1; 238 239 /* 240 * set up the chipset's info; done once at console init time 241 * (maybe), but we must do it here as well to take care of things 242 * that need to use memory allocation. 243 */ 244 ccp = sc->sc_ccp = &cia_configuration; 245 cia_init(ccp, 1); 246 247 if (ccp->cc_flags & CCF_ISPYXIS) { 248 name = "Pyxis"; 249 pass = ccp->cc_rev; 250 } else { 251 name = "ALCOR/ALCOR2"; 252 pass = ccp->cc_rev + 1; 253 } 254 255 printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n", 256 name, pass); 257 if (ccp->cc_cnfg) 258 printf("%s: extended capabilities: %s\n", self->dv_xname, 259 bitmask_snprintf(ccp->cc_cnfg, CIA_CSR_CNFG_BITS, 260 bits, sizeof(bits))); 261 #if 1 262 if (ccp->cc_flags & CCF_USEBWX) 263 printf("%s: using BWX for PCI config and device access\n", 264 self->dv_xname); 265 #endif 266 267 #ifdef DEC_550 268 if (hwrpb->rpb_type == ST_DEC_550 && 269 (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 270 /* 271 * Miata 1 systems have a bug: DMA cannot cross 272 * an 8k boundary! Make sure PCI read prefetching 273 * is disabled on these chips. Note that secondary 274 * PCI busses don't have this problem, because of 275 * the way PPBs handle PCI read requests. 276 * 277 * In the 21174 Technical Reference Manual, this is 278 * actually documented as "Pyxis Pass 1", but apparently 279 * there are chips that report themselves as "Pass 1" 280 * which do not have the bug! Miatas with the Cypress 281 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not 282 * have the bug, so we use this check. 283 * 284 * XXX We also need to deal with this boundary constraint 285 * XXX in the PCI bus 0 (and ISA) DMA tags, but some 286 * XXX drivers are going to need to be changed first. 287 */ 288 u_int32_t ctrl; 289 290 /* XXX no bets... */ 291 printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n", 292 self->dv_xname); 293 294 alpha_mb(); 295 ctrl = REGVAL(CIA_CSR_CTRL); 296 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE); 297 REGVAL(CIA_CSR_CTRL) = ctrl; 298 alpha_mb(); 299 } 300 #endif /* DEC_550 */ 301 302 cia_dma_init(ccp); 303 304 switch (hwrpb->rpb_type) { 305 #ifdef DEC_KN20AA 306 case ST_DEC_KN20AA: 307 pci_kn20aa_pickintr(ccp); 308 #ifdef EVCNT_COUNTERS 309 evcnt_attach(self, "intr", &kn20aa_intr_evcnt); 310 #endif 311 break; 312 #endif 313 314 #ifdef DEC_EB164 315 case ST_EB164: 316 pci_eb164_pickintr(ccp); 317 #ifdef EVCNT_COUNTERS 318 evcnt_attach(self, "intr", &eb164_intr_evcnt); 319 #endif 320 break; 321 #endif 322 323 #ifdef DEC_550 324 case ST_DEC_550: 325 pci_550_pickintr(ccp); 326 #ifdef EVCNT_COUNTERS 327 evcnt_attach(self, "intr", &dec_550_intr_evcnt); 328 #endif 329 break; 330 #endif 331 332 default: 333 panic("ciaattach: shouldn't be here, really..."); 334 } 335 336 pba.pba_busname = "pci"; 337 pba.pba_iot = &ccp->cc_iot; 338 pba.pba_memt = &ccp->cc_memt; 339 pba.pba_dmat = 340 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI); 341 pba.pba_pc = &ccp->cc_pc; 342 pba.pba_bus = 0; 343 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 344 config_found(self, &pba, ciaprint); 345 } 346 347 static int 348 ciaprint(aux, pnp) 349 void *aux; 350 const char *pnp; 351 { 352 register struct pcibus_attach_args *pba = aux; 353 354 /* only PCIs can attach to CIAs; easy. */ 355 if (pnp) 356 printf("%s at %s", pba->pba_busname, pnp); 357 printf(" bus %d", pba->pba_bus); 358 return (UNCONF); 359 } 360
Indexes created Tue Sep 30 17:09:57 GMT 2025