cia.c revision 1.44
1 /* $NetBSD: cia.c,v 1.44 1998/06/24 01:32:06 ross Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_eb164.h" 68 #include "opt_dec_kn20aa.h" 69 #include "opt_dec_550.h" 70 #include "opt_dec_1000a.h" 71 72 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 73 74 __KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.44 1998/06/24 01:32:06 ross Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/malloc.h> 80 #include <sys/device.h> 81 #include <vm/vm.h> 82 83 #include <machine/autoconf.h> 84 #include <machine/rpb.h> 85 86 #include <dev/isa/isareg.h> 87 #include <dev/isa/isavar.h> 88 89 #include <dev/pci/pcireg.h> 90 #include <dev/pci/pcivar.h> 91 #include <alpha/pci/ciareg.h> 92 #include <alpha/pci/ciavar.h> 93 #ifdef DEC_KN20AA 94 #include <alpha/pci/pci_kn20aa.h> 95 #endif 96 #ifdef DEC_EB164 97 #include <alpha/pci/pci_eb164.h> 98 #endif 99 #ifdef DEC_550 100 #include <alpha/pci/pci_550.h> 101 #endif 102 #ifdef DEC_1000A 103 #include <alpha/pci/pci_1000a.h> 104 #endif 105 106 int ciamatch __P((struct device *, struct cfdata *, void *)); 107 void ciaattach __P((struct device *, struct device *, void *)); 108 109 struct cfattach cia_ca = { 110 sizeof(struct cia_softc), ciamatch, ciaattach, 111 }; 112 113 extern struct cfdriver cia_cd; 114 115 static int ciaprint __P((void *, const char *pnp)); 116 117 /* There can be only one. */ 118 int ciafound; 119 struct cia_config cia_configuration; 120 121 /* 122 * This determines if we attempt to use BWX for PCI bus and config space 123 * access. Some systems, notably with Pyxis, don't fare so well unless 124 * BWX is used. 125 */ 126 #ifndef CIA_USE_BWX 127 #define CIA_USE_BWX 1 128 #endif 129 130 int cia_use_bwx = CIA_USE_BWX; 131 132 int 133 ciamatch(parent, match, aux) 134 struct device *parent; 135 struct cfdata *match; 136 void *aux; 137 { 138 struct mainbus_attach_args *ma = aux; 139 140 /* Make sure that we're looking for a CIA. */ 141 if (strcmp(ma->ma_name, cia_cd.cd_name) != 0) 142 return (0); 143 144 if (ciafound) 145 return (0); 146 147 return (1); 148 } 149 150 /* 151 * Set up the chipset's function pointers. 152 */ 153 void 154 cia_init(ccp, mallocsafe) 155 struct cia_config *ccp; 156 int mallocsafe; 157 { 158 159 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM); 160 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO); 161 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK; 162 163 /* 164 * Determine if we have a Pyxis. Only two systypes can 165 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX) 166 * and the DEC_550 systype (Miata). 167 */ 168 if ((hwrpb->rpb_type == ST_EB164 && 169 (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) || 170 hwrpb->rpb_type == ST_DEC_550) 171 ccp->cc_flags |= CCF_ISPYXIS; 172 173 /* 174 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register. 175 */ 176 if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0) 177 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG); 178 else 179 ccp->cc_cnfg = 0; 180 181 /* 182 * Use BWX iff: 183 * 184 * - It hasn't been disbled by the user, 185 * - it's enabled in CNFG, 186 * - we're implementation version ev5, 187 * - BWX is enabled in the CPU's capabilities mask (yes, 188 * the bit is really cleared if the capability exists...) 189 */ 190 if (cia_use_bwx != 0 && 191 (ccp->cc_cnfg & CNFG_BWEN) != 0 && 192 alpha_implver() == ALPHA_IMPLVER_EV5 && 193 alpha_amask(ALPHA_AMASK_BWX) == 0) { 194 u_int32_t ctrl; 195 196 ccp->cc_flags |= CCF_USEBWX; 197 198 /* 199 * For whatever reason, the firmware seems to enable PCI 200 * loopback mode if it also enables BWX. Make sure it's 201 * enabled if we have an old, buggy firmware rev. 202 */ 203 alpha_mb(); 204 ctrl = REGVAL(CIA_CSR_CTRL); 205 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) { 206 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 207 alpha_mb(); 208 } 209 } 210 211 if (!ccp->cc_initted) { 212 /* don't do these twice since they set up extents */ 213 if (ccp->cc_flags & CCF_USEBWX) { 214 cia_bwx_bus_io_init(&ccp->cc_iot, ccp); 215 cia_bwx_bus_mem_init(&ccp->cc_memt, ccp); 216 } else { 217 cia_swiz_bus_io_init(&ccp->cc_iot, ccp); 218 cia_swiz_bus_mem_init(&ccp->cc_memt, ccp); 219 } 220 } 221 ccp->cc_mallocsafe = mallocsafe; 222 223 cia_pci_init(&ccp->cc_pc, ccp); 224 225 ccp->cc_initted = 1; 226 } 227 228 void 229 ciaattach(parent, self, aux) 230 struct device *parent, *self; 231 void *aux; 232 { 233 struct cia_softc *sc = (struct cia_softc *)self; 234 struct cia_config *ccp; 235 struct pcibus_attach_args pba; 236 char bits[64]; 237 const char *name; 238 int pass; 239 240 /* note that we've attached the chipset; can't have 2 CIAs. */ 241 ciafound = 1; 242 243 /* 244 * set up the chipset's info; done once at console init time 245 * (maybe), but we must do it here as well to take care of things 246 * that need to use memory allocation. 247 */ 248 ccp = sc->sc_ccp = &cia_configuration; 249 cia_init(ccp, 1); 250 251 if (ccp->cc_flags & CCF_ISPYXIS) { 252 name = "Pyxis"; 253 pass = ccp->cc_rev; 254 } else { 255 name = "ALCOR/ALCOR2"; 256 pass = ccp->cc_rev + 1; 257 } 258 259 printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n", 260 name, pass); 261 if (ccp->cc_cnfg) 262 printf("%s: extended capabilities: %s\n", self->dv_xname, 263 bitmask_snprintf(ccp->cc_cnfg, CIA_CSR_CNFG_BITS, 264 bits, sizeof(bits))); 265 #if 1 266 if (ccp->cc_flags & CCF_USEBWX) 267 printf("%s: using BWX for PCI config and device access\n", 268 self->dv_xname); 269 #endif 270 271 #ifdef DEC_550 272 if (hwrpb->rpb_type == ST_DEC_550 && 273 (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 274 /* 275 * Miata 1 systems have a bug: DMA cannot cross 276 * an 8k boundary! Make sure PCI read prefetching 277 * is disabled on these chips. Note that secondary 278 * PCI busses don't have this problem, because of 279 * the way PPBs handle PCI read requests. 280 * 281 * In the 21174 Technical Reference Manual, this is 282 * actually documented as "Pyxis Pass 1", but apparently 283 * there are chips that report themselves as "Pass 1" 284 * which do not have the bug! Miatas with the Cypress 285 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not 286 * have the bug, so we use this check. 287 * 288 * XXX We also need to deal with this boundary constraint 289 * XXX in the PCI bus 0 (and ISA) DMA tags, but some 290 * XXX drivers are going to need to be changed first. 291 */ 292 u_int32_t ctrl; 293 294 /* XXX no bets... */ 295 printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n", 296 self->dv_xname); 297 298 alpha_mb(); 299 ctrl = REGVAL(CIA_CSR_CTRL); 300 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE); 301 REGVAL(CIA_CSR_CTRL) = ctrl; 302 alpha_mb(); 303 } 304 #endif /* DEC_550 */ 305 306 cia_dma_init(ccp); 307 308 switch (hwrpb->rpb_type) { 309 #ifdef DEC_KN20AA 310 case ST_DEC_KN20AA: 311 pci_kn20aa_pickintr(ccp); 312 #ifdef EVCNT_COUNTERS 313 evcnt_attach(self, "intr", &kn20aa_intr_evcnt); 314 #endif 315 break; 316 #endif 317 318 #ifdef DEC_EB164 319 case ST_EB164: 320 pci_eb164_pickintr(ccp); 321 #ifdef EVCNT_COUNTERS 322 evcnt_attach(self, "intr", &eb164_intr_evcnt); 323 #endif 324 break; 325 #endif 326 327 #ifdef DEC_550 328 case ST_DEC_550: 329 pci_550_pickintr(ccp); 330 #ifdef EVCNT_COUNTERS 331 evcnt_attach(self, "intr", &dec_550_intr_evcnt); 332 #endif 333 break; 334 #endif 335 336 #ifdef DEC_1000A 337 case ST_DEC_1000A: 338 pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 339 &ccp->cc_pc); 340 #ifdef EVCNT_COUNTERS 341 evcnt_attach(self, "intr", &dec_1000a_intr_evcnt); 342 #endif 343 break; 344 #endif 345 346 default: 347 panic("ciaattach: shouldn't be here, really..."); 348 } 349 350 pba.pba_busname = "pci"; 351 pba.pba_iot = &ccp->cc_iot; 352 pba.pba_memt = &ccp->cc_memt; 353 pba.pba_dmat = 354 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI); 355 pba.pba_pc = &ccp->cc_pc; 356 pba.pba_bus = 0; 357 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 358 config_found(self, &pba, ciaprint); 359 } 360 361 static int 362 ciaprint(aux, pnp) 363 void *aux; 364 const char *pnp; 365 { 366 register struct pcibus_attach_args *pba = aux; 367 368 /* only PCIs can attach to CIAs; easy. */ 369 if (pnp) 370 printf("%s at %s", pba->pba_busname, pnp); 371 printf(" bus %d", pba->pba_bus); 372 return (UNCONF); 373 } 374
Indexes created Tue Sep 30 20:09:53 GMT 2025