cia.c revision 1.45
1 /* $NetBSD: cia.c,v 1.45 1998/06/26 21:45:56 ross Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_eb164.h" 68 #include "opt_dec_kn20aa.h" 69 #include "opt_dec_550.h" 70 #include "opt_dec_1000a.h" 71 #include "opt_dec_1000.h" 72 73 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 74 75 __KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.45 1998/06/26 21:45:56 ross Exp $"); 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/kernel.h> 80 #include <sys/malloc.h> 81 #include <sys/device.h> 82 #include <vm/vm.h> 83 84 #include <machine/autoconf.h> 85 #include <machine/rpb.h> 86 87 #include <dev/isa/isareg.h> 88 #include <dev/isa/isavar.h> 89 90 #include <dev/pci/pcireg.h> 91 #include <dev/pci/pcivar.h> 92 #include <alpha/pci/ciareg.h> 93 #include <alpha/pci/ciavar.h> 94 95 #ifdef DEC_KN20AA 96 #include <alpha/pci/pci_kn20aa.h> 97 #endif 98 #ifdef DEC_EB164 99 #include <alpha/pci/pci_eb164.h> 100 #endif 101 #ifdef DEC_550 102 #include <alpha/pci/pci_550.h> 103 #endif 104 #ifdef DEC_1000A 105 #include <alpha/pci/pci_1000a.h> 106 #endif 107 #ifdef DEC_1000 108 #include <alpha/pci/pci_1000.h> 109 #endif 110 111 int ciamatch __P((struct device *, struct cfdata *, void *)); 112 void ciaattach __P((struct device *, struct device *, void *)); 113 114 struct cfattach cia_ca = { 115 sizeof(struct cia_softc), ciamatch, ciaattach, 116 }; 117 118 extern struct cfdriver cia_cd; 119 120 static int ciaprint __P((void *, const char *pnp)); 121 122 /* There can be only one. */ 123 int ciafound; 124 struct cia_config cia_configuration; 125 126 /* 127 * This determines if we attempt to use BWX for PCI bus and config space 128 * access. Some systems, notably with Pyxis, don't fare so well unless 129 * BWX is used. 130 */ 131 #ifndef CIA_USE_BWX 132 #define CIA_USE_BWX 1 133 #endif 134 135 int cia_use_bwx = CIA_USE_BWX; 136 137 int 138 ciamatch(parent, match, aux) 139 struct device *parent; 140 struct cfdata *match; 141 void *aux; 142 { 143 struct mainbus_attach_args *ma = aux; 144 145 /* Make sure that we're looking for a CIA. */ 146 if (strcmp(ma->ma_name, cia_cd.cd_name) != 0) 147 return (0); 148 149 if (ciafound) 150 return (0); 151 152 return (1); 153 } 154 155 /* 156 * Set up the chipset's function pointers. 157 */ 158 void 159 cia_init(ccp, mallocsafe) 160 struct cia_config *ccp; 161 int mallocsafe; 162 { 163 164 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM); 165 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO); 166 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK; 167 168 /* 169 * Determine if we have a Pyxis. Only two systypes can 170 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX) 171 * and the DEC_550 systype (Miata). 172 */ 173 if ((hwrpb->rpb_type == ST_EB164 && 174 (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) || 175 hwrpb->rpb_type == ST_DEC_550) 176 ccp->cc_flags |= CCF_ISPYXIS; 177 178 /* 179 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register. 180 */ 181 if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0) 182 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG); 183 else 184 ccp->cc_cnfg = 0; 185 186 /* 187 * Use BWX iff: 188 * 189 * - It hasn't been disbled by the user, 190 * - it's enabled in CNFG, 191 * - we're implementation version ev5, 192 * - BWX is enabled in the CPU's capabilities mask (yes, 193 * the bit is really cleared if the capability exists...) 194 */ 195 if (cia_use_bwx != 0 && 196 (ccp->cc_cnfg & CNFG_BWEN) != 0 && 197 alpha_implver() == ALPHA_IMPLVER_EV5 && 198 alpha_amask(ALPHA_AMASK_BWX) == 0) { 199 u_int32_t ctrl; 200 201 ccp->cc_flags |= CCF_USEBWX; 202 203 /* 204 * For whatever reason, the firmware seems to enable PCI 205 * loopback mode if it also enables BWX. Make sure it's 206 * enabled if we have an old, buggy firmware rev. 207 */ 208 alpha_mb(); 209 ctrl = REGVAL(CIA_CSR_CTRL); 210 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) { 211 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 212 alpha_mb(); 213 } 214 } 215 216 if (!ccp->cc_initted) { 217 /* don't do these twice since they set up extents */ 218 if (ccp->cc_flags & CCF_USEBWX) { 219 cia_bwx_bus_io_init(&ccp->cc_iot, ccp); 220 cia_bwx_bus_mem_init(&ccp->cc_memt, ccp); 221 } else { 222 cia_swiz_bus_io_init(&ccp->cc_iot, ccp); 223 cia_swiz_bus_mem_init(&ccp->cc_memt, ccp); 224 } 225 } 226 ccp->cc_mallocsafe = mallocsafe; 227 228 cia_pci_init(&ccp->cc_pc, ccp); 229 230 ccp->cc_initted = 1; 231 } 232 233 void 234 ciaattach(parent, self, aux) 235 struct device *parent, *self; 236 void *aux; 237 { 238 struct cia_softc *sc = (struct cia_softc *)self; 239 struct cia_config *ccp; 240 struct pcibus_attach_args pba; 241 char bits[64]; 242 const char *name; 243 int pass; 244 245 /* note that we've attached the chipset; can't have 2 CIAs. */ 246 ciafound = 1; 247 248 /* 249 * set up the chipset's info; done once at console init time 250 * (maybe), but we must do it here as well to take care of things 251 * that need to use memory allocation. 252 */ 253 ccp = sc->sc_ccp = &cia_configuration; 254 cia_init(ccp, 1); 255 256 if (ccp->cc_flags & CCF_ISPYXIS) { 257 name = "Pyxis"; 258 pass = ccp->cc_rev; 259 } else { 260 name = "ALCOR/ALCOR2"; 261 pass = ccp->cc_rev + 1; 262 } 263 264 printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n", 265 name, pass); 266 if (ccp->cc_cnfg) 267 printf("%s: extended capabilities: %s\n", self->dv_xname, 268 bitmask_snprintf(ccp->cc_cnfg, CIA_CSR_CNFG_BITS, 269 bits, sizeof(bits))); 270 #if 1 271 if (ccp->cc_flags & CCF_USEBWX) 272 printf("%s: using BWX for PCI config and device access\n", 273 self->dv_xname); 274 #endif 275 276 #ifdef DEC_550 277 if (hwrpb->rpb_type == ST_DEC_550 && 278 (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 279 /* 280 * Miata 1 systems have a bug: DMA cannot cross 281 * an 8k boundary! Make sure PCI read prefetching 282 * is disabled on these chips. Note that secondary 283 * PCI busses don't have this problem, because of 284 * the way PPBs handle PCI read requests. 285 * 286 * In the 21174 Technical Reference Manual, this is 287 * actually documented as "Pyxis Pass 1", but apparently 288 * there are chips that report themselves as "Pass 1" 289 * which do not have the bug! Miatas with the Cypress 290 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not 291 * have the bug, so we use this check. 292 * 293 * XXX We also need to deal with this boundary constraint 294 * XXX in the PCI bus 0 (and ISA) DMA tags, but some 295 * XXX drivers are going to need to be changed first. 296 */ 297 u_int32_t ctrl; 298 299 /* XXX no bets... */ 300 printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n", 301 self->dv_xname); 302 303 alpha_mb(); 304 ctrl = REGVAL(CIA_CSR_CTRL); 305 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE); 306 REGVAL(CIA_CSR_CTRL) = ctrl; 307 alpha_mb(); 308 } 309 #endif /* DEC_550 */ 310 311 cia_dma_init(ccp); 312 313 switch (hwrpb->rpb_type) { 314 #ifdef DEC_KN20AA 315 case ST_DEC_KN20AA: 316 pci_kn20aa_pickintr(ccp); 317 break; 318 #endif 319 320 #ifdef DEC_EB164 321 case ST_EB164: 322 pci_eb164_pickintr(ccp); 323 break; 324 #endif 325 326 #ifdef DEC_550 327 case ST_DEC_550: 328 pci_550_pickintr(ccp); 329 break; 330 #endif 331 332 #ifdef DEC_1000A 333 case ST_DEC_1000A: 334 pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 335 &ccp->cc_pc); 336 break; 337 #endif 338 339 #ifdef DEC_1000 340 case ST_DEC_1000: 341 pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 342 &ccp->cc_pc); 343 break; 344 #endif 345 346 default: 347 panic("ciaattach: shouldn't be here, really..."); 348 } 349 350 pba.pba_busname = "pci"; 351 pba.pba_iot = &ccp->cc_iot; 352 pba.pba_memt = &ccp->cc_memt; 353 pba.pba_dmat = 354 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI); 355 pba.pba_pc = &ccp->cc_pc; 356 pba.pba_bus = 0; 357 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 358 config_found(self, &pba, ciaprint); 359 } 360 361 static int 362 ciaprint(aux, pnp) 363 void *aux; 364 const char *pnp; 365 { 366 register struct pcibus_attach_args *pba = aux; 367 368 /* only PCIs can attach to CIAs; easy. */ 369 if (pnp) 370 printf("%s at %s", pba->pba_busname, pnp); 371 printf(" bus %d", pba->pba_bus); 372 return (UNCONF); 373 } 374
Indexes created Tue Sep 30 11:09:46 GMT 2025