cia.c revision 1.49
1 /* $NetBSD: cia.c,v 1.49 1999/11/04 19:11:51 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_eb164.h" 68 #include "opt_dec_kn20aa.h" 69 #include "opt_dec_550.h" 70 #include "opt_dec_1000a.h" 71 #include "opt_dec_1000.h" 72 73 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 74 75 __KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.49 1999/11/04 19:11:51 thorpej Exp $"); 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/kernel.h> 80 #include <sys/malloc.h> 81 #include <sys/device.h> 82 #include <vm/vm.h> 83 84 #include <machine/autoconf.h> 85 #include <machine/rpb.h> 86 87 #include <dev/isa/isareg.h> 88 #include <dev/isa/isavar.h> 89 90 #include <dev/pci/pcireg.h> 91 #include <dev/pci/pcivar.h> 92 #include <alpha/pci/ciareg.h> 93 #include <alpha/pci/ciavar.h> 94 95 #ifdef DEC_KN20AA 96 #include <alpha/pci/pci_kn20aa.h> 97 #endif 98 #ifdef DEC_EB164 99 #include <alpha/pci/pci_eb164.h> 100 #endif 101 #ifdef DEC_550 102 #include <alpha/pci/pci_550.h> 103 #endif 104 #ifdef DEC_1000A 105 #include <alpha/pci/pci_1000a.h> 106 #endif 107 #ifdef DEC_1000 108 #include <alpha/pci/pci_1000.h> 109 #endif 110 111 int ciamatch __P((struct device *, struct cfdata *, void *)); 112 void ciaattach __P((struct device *, struct device *, void *)); 113 114 struct cfattach cia_ca = { 115 sizeof(struct cia_softc), ciamatch, ciaattach, 116 }; 117 118 extern struct cfdriver cia_cd; 119 120 static int ciaprint __P((void *, const char *pnp)); 121 122 /* There can be only one. */ 123 int ciafound; 124 struct cia_config cia_configuration; 125 126 /* 127 * This determines if we attempt to use BWX for PCI bus and config space 128 * access. Some systems, notably with Pyxis, don't fare so well unless 129 * BWX is used. 130 * 131 * EXCEPT! Some devices have a really hard time if BWX is used (WHY?!). 132 * So, we decouple the uses for PCI config space and PCI bus space. 133 */ 134 135 #ifndef CIA_PCI_USE_BWX 136 #define CIA_PCI_USE_BWX 1 137 #endif 138 139 #ifndef CIA_BUS_USE_BWX 140 #define CIA_BUS_USE_BWX 0 141 #endif 142 143 int cia_pci_use_bwx = CIA_PCI_USE_BWX; 144 int cia_bus_use_bwx = CIA_BUS_USE_BWX; 145 146 int 147 ciamatch(parent, match, aux) 148 struct device *parent; 149 struct cfdata *match; 150 void *aux; 151 { 152 struct mainbus_attach_args *ma = aux; 153 154 /* Make sure that we're looking for a CIA. */ 155 if (strcmp(ma->ma_name, cia_cd.cd_name) != 0) 156 return (0); 157 158 if (ciafound) 159 return (0); 160 161 return (1); 162 } 163 164 /* 165 * Set up the chipset's function pointers. 166 */ 167 void 168 cia_init(ccp, mallocsafe) 169 struct cia_config *ccp; 170 int mallocsafe; 171 { 172 173 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM); 174 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO); 175 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK; 176 177 /* 178 * Determine if we have a Pyxis. Only two systypes can 179 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX) 180 * and the DEC_550 systype (Miata). 181 */ 182 if ((cputype == ST_EB164 && 183 (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) || 184 cputype == ST_DEC_550) 185 ccp->cc_flags |= CCF_ISPYXIS; 186 187 /* 188 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register. 189 */ 190 if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0) 191 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG); 192 else 193 ccp->cc_cnfg = 0; 194 195 /* 196 * Use BWX iff: 197 * 198 * - It hasn't been disbled by the user, 199 * - it's enabled in CNFG, 200 * - we're implementation version ev5, 201 * - BWX is enabled in the CPU's capabilities mask (yes, 202 * the bit is really cleared if the capability exists...) 203 */ 204 if ((cia_pci_use_bwx || cia_bus_use_bwx) && 205 (ccp->cc_cnfg & CNFG_BWEN) != 0 && 206 alpha_implver() == ALPHA_IMPLVER_EV5 && 207 alpha_amask(ALPHA_AMASK_BWX) == 0) { 208 u_int32_t ctrl; 209 210 if (cia_pci_use_bwx) 211 ccp->cc_flags |= CCF_PCI_USE_BWX; 212 if (cia_bus_use_bwx) 213 ccp->cc_flags |= CCF_BUS_USE_BWX; 214 215 /* 216 * For whatever reason, the firmware seems to enable PCI 217 * loopback mode if it also enables BWX. Make sure it's 218 * enabled if we have an old, buggy firmware rev. 219 */ 220 alpha_mb(); 221 ctrl = REGVAL(CIA_CSR_CTRL); 222 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) { 223 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 224 alpha_mb(); 225 } 226 } 227 228 if (!ccp->cc_initted) { 229 /* don't do these twice since they set up extents */ 230 if (ccp->cc_flags & CCF_BUS_USE_BWX) { 231 cia_bwx_bus_io_init(&ccp->cc_iot, ccp); 232 cia_bwx_bus_mem_init(&ccp->cc_memt, ccp); 233 } else { 234 cia_swiz_bus_io_init(&ccp->cc_iot, ccp); 235 cia_swiz_bus_mem_init(&ccp->cc_memt, ccp); 236 } 237 } 238 ccp->cc_mallocsafe = mallocsafe; 239 240 cia_pci_init(&ccp->cc_pc, ccp); 241 242 ccp->cc_initted = 1; 243 } 244 245 void 246 ciaattach(parent, self, aux) 247 struct device *parent, *self; 248 void *aux; 249 { 250 struct cia_softc *sc = (struct cia_softc *)self; 251 struct cia_config *ccp; 252 struct pcibus_attach_args pba; 253 char bits[64]; 254 const char *name; 255 int pass; 256 257 /* note that we've attached the chipset; can't have 2 CIAs. */ 258 ciafound = 1; 259 260 /* 261 * set up the chipset's info; done once at console init time 262 * (maybe), but we must do it here as well to take care of things 263 * that need to use memory allocation. 264 */ 265 ccp = sc->sc_ccp = &cia_configuration; 266 cia_init(ccp, 1); 267 268 if (ccp->cc_flags & CCF_ISPYXIS) { 269 name = "Pyxis"; 270 pass = ccp->cc_rev; 271 } else { 272 name = "ALCOR/ALCOR2"; 273 pass = ccp->cc_rev + 1; 274 } 275 276 printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n", 277 name, pass); 278 if (ccp->cc_cnfg) 279 printf("%s: extended capabilities: %s\n", self->dv_xname, 280 bitmask_snprintf(ccp->cc_cnfg, CIA_CSR_CNFG_BITS, 281 bits, sizeof(bits))); 282 283 switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) { 284 case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX: 285 name = "PCI config and bus"; 286 break; 287 case CCF_PCI_USE_BWX: 288 name = "PCI config"; 289 break; 290 case CCF_BUS_USE_BWX: 291 name = "bus"; 292 break; 293 default: 294 name = NULL; 295 break; 296 } 297 if (name != NULL) 298 printf("%s: using BWX for %s access\n", self->dv_xname, name); 299 300 #ifdef DEC_550 301 if (cputype == ST_DEC_550 && 302 (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 303 /* 304 * Miata 1 systems have a bug: DMA cannot cross 305 * an 8k boundary! Make sure PCI read prefetching 306 * is disabled on these chips. Note that secondary 307 * PCI busses don't have this problem, because of 308 * the way PPBs handle PCI read requests. 309 * 310 * In the 21174 Technical Reference Manual, this is 311 * actually documented as "Pyxis Pass 1", but apparently 312 * there are chips that report themselves as "Pass 1" 313 * which do not have the bug! Miatas with the Cypress 314 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not 315 * have the bug, so we use this check. 316 * 317 * XXX We also need to deal with this boundary constraint 318 * XXX in the PCI bus 0 (and ISA) DMA tags, but some 319 * XXX drivers are going to need to be changed first. 320 */ 321 u_int32_t ctrl; 322 323 /* XXX no bets... */ 324 printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n", 325 self->dv_xname); 326 327 ccp->cc_flags |= CCF_PYXISBUG; 328 329 alpha_mb(); 330 ctrl = REGVAL(CIA_CSR_CTRL); 331 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE); 332 REGVAL(CIA_CSR_CTRL) = ctrl; 333 alpha_mb(); 334 } 335 #endif /* DEC_550 */ 336 337 cia_dma_init(ccp); 338 339 switch (cputype) { 340 #ifdef DEC_KN20AA 341 case ST_DEC_KN20AA: 342 pci_kn20aa_pickintr(ccp); 343 break; 344 #endif 345 346 #ifdef DEC_EB164 347 case ST_EB164: 348 pci_eb164_pickintr(ccp); 349 break; 350 #endif 351 352 #ifdef DEC_550 353 case ST_DEC_550: 354 pci_550_pickintr(ccp); 355 break; 356 #endif 357 358 #ifdef DEC_1000A 359 case ST_DEC_1000A: 360 pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 361 &ccp->cc_pc); 362 break; 363 #endif 364 365 #ifdef DEC_1000 366 case ST_DEC_1000: 367 pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 368 &ccp->cc_pc); 369 break; 370 #endif 371 372 default: 373 panic("ciaattach: shouldn't be here, really..."); 374 } 375 376 pba.pba_busname = "pci"; 377 pba.pba_iot = &ccp->cc_iot; 378 pba.pba_memt = &ccp->cc_memt; 379 pba.pba_dmat = 380 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI); 381 pba.pba_pc = &ccp->cc_pc; 382 pba.pba_bus = 0; 383 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 384 if ((ccp->cc_flags & CCF_PYXISBUG) == 0) 385 pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | 386 PCI_FLAGS_MWI_OKAY; 387 config_found(self, &pba, ciaprint); 388 } 389 390 static int 391 ciaprint(aux, pnp) 392 void *aux; 393 const char *pnp; 394 { 395 register struct pcibus_attach_args *pba = aux; 396 397 /* only PCIs can attach to CIAs; easy. */ 398 if (pnp) 399 printf("%s at %s", pba->pba_busname, pnp); 400 printf(" bus %d", pba->pba_bus); 401 return (UNCONF); 402 } 403
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