cia.c revision 1.62
1 /* $NetBSD: cia.c,v 1.62 2003/06/15 23:08:54 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_eb164.h" 68 #include "opt_dec_kn20aa.h" 69 #include "opt_dec_550.h" 70 #include "opt_dec_1000a.h" 71 #include "opt_dec_1000.h" 72 73 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 74 75 __KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.62 2003/06/15 23:08:54 fvdl Exp $"); 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/kernel.h> 80 #include <sys/malloc.h> 81 #include <sys/device.h> 82 83 #include <uvm/uvm_extern.h> 84 85 #include <machine/autoconf.h> 86 #include <machine/rpb.h> 87 #include <machine/sysarch.h> 88 #include <machine/alpha.h> 89 90 #include <dev/isa/isareg.h> 91 #include <dev/isa/isavar.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 #include <alpha/pci/ciareg.h> 96 #include <alpha/pci/ciavar.h> 97 98 #ifdef DEC_KN20AA 99 #include <alpha/pci/pci_kn20aa.h> 100 #endif 101 #ifdef DEC_EB164 102 #include <alpha/pci/pci_eb164.h> 103 #endif 104 #ifdef DEC_550 105 #include <alpha/pci/pci_550.h> 106 #endif 107 #ifdef DEC_1000A 108 #include <alpha/pci/pci_1000a.h> 109 #endif 110 #ifdef DEC_1000 111 #include <alpha/pci/pci_1000.h> 112 #endif 113 114 int ciamatch __P((struct device *, struct cfdata *, void *)); 115 void ciaattach __P((struct device *, struct device *, void *)); 116 117 CFATTACH_DECL(cia, sizeof(struct cia_softc), 118 ciamatch, ciaattach, NULL, NULL); 119 120 extern struct cfdriver cia_cd; 121 122 static int ciaprint __P((void *, const char *pnp)); 123 124 int cia_bus_get_window __P((int, int, 125 struct alpha_bus_space_translation *)); 126 127 /* There can be only one. */ 128 int ciafound; 129 struct cia_config cia_configuration; 130 131 /* 132 * This determines if we attempt to use BWX for PCI bus and config space 133 * access. Some systems, notably with Pyxis, don't fare so well unless 134 * BWX is used. 135 * 136 * EXCEPT! Some devices have a really hard time if BWX is used (WHY?!). 137 * So, we decouple the uses for PCI config space and PCI bus space. 138 * 139 * FURTHERMORE! The Pyxis, most notably earlier revs, really don't 140 * do so well if you don't use BWX for bus access. So we default to 141 * forcing BWX on those chips. 142 * 143 * Geez. 144 */ 145 146 #ifndef CIA_PCI_USE_BWX 147 #define CIA_PCI_USE_BWX 1 148 #endif 149 150 #ifndef CIA_BUS_USE_BWX 151 #define CIA_BUS_USE_BWX 0 152 #endif 153 154 #ifndef CIA_PYXIS_FORCE_BWX 155 #define CIA_PYXIS_FORCE_BWX 0 156 #endif 157 158 int cia_pci_use_bwx = CIA_PCI_USE_BWX; 159 int cia_bus_use_bwx = CIA_BUS_USE_BWX; 160 int cia_pyxis_force_bwx = CIA_PYXIS_FORCE_BWX; 161 162 int 163 ciamatch(parent, match, aux) 164 struct device *parent; 165 struct cfdata *match; 166 void *aux; 167 { 168 struct mainbus_attach_args *ma = aux; 169 170 /* Make sure that we're looking for a CIA. */ 171 if (strcmp(ma->ma_name, cia_cd.cd_name) != 0) 172 return (0); 173 174 if (ciafound) 175 return (0); 176 177 return (1); 178 } 179 180 /* 181 * Set up the chipset's function pointers. 182 */ 183 void 184 cia_init(ccp, mallocsafe) 185 struct cia_config *ccp; 186 int mallocsafe; 187 { 188 int pci_use_bwx = cia_pci_use_bwx; 189 int bus_use_bwx = cia_bus_use_bwx; 190 191 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM); 192 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO); 193 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK; 194 195 /* 196 * Determine if we have a Pyxis. Only two systypes can 197 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX) 198 * and the DEC_550 systype (Miata). 199 */ 200 if ((cputype == ST_EB164 && 201 (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) || 202 cputype == ST_DEC_550) { 203 ccp->cc_flags |= CCF_ISPYXIS; 204 if (cia_pyxis_force_bwx) 205 pci_use_bwx = bus_use_bwx = 1; 206 } 207 208 /* 209 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register. 210 */ 211 if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0) 212 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG); 213 else 214 ccp->cc_cnfg = 0; 215 216 /* 217 * Use BWX iff: 218 * 219 * - It hasn't been disbled by the user, 220 * - it's enabled in CNFG, 221 * - we're implementation version ev5, 222 * - BWX is enabled in the CPU's capabilities mask 223 */ 224 if ((pci_use_bwx || bus_use_bwx) && 225 (ccp->cc_cnfg & CNFG_BWEN) != 0 && 226 (cpu_amask & ALPHA_AMASK_BWX) != 0) { 227 u_int32_t ctrl; 228 229 if (pci_use_bwx) 230 ccp->cc_flags |= CCF_PCI_USE_BWX; 231 if (bus_use_bwx) 232 ccp->cc_flags |= CCF_BUS_USE_BWX; 233 234 /* 235 * For whatever reason, the firmware seems to enable PCI 236 * loopback mode if it also enables BWX. Make sure it's 237 * enabled if we have an old, buggy firmware rev. 238 */ 239 alpha_mb(); 240 ctrl = REGVAL(CIA_CSR_CTRL); 241 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) { 242 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 243 alpha_mb(); 244 } 245 } 246 247 if (!ccp->cc_initted) { 248 /* don't do these twice since they set up extents */ 249 if (ccp->cc_flags & CCF_BUS_USE_BWX) { 250 cia_bwx_bus_io_init(&ccp->cc_iot, ccp); 251 cia_bwx_bus_mem_init(&ccp->cc_memt, ccp); 252 253 /* 254 * We have one window for both PCI I/O and MEM 255 * in BWX mode. 256 */ 257 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1; 258 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1; 259 } else { 260 cia_swiz_bus_io_init(&ccp->cc_iot, ccp); 261 cia_swiz_bus_mem_init(&ccp->cc_memt, ccp); 262 263 /* 264 * We have two I/O windows and 4 MEM windows in 265 * SWIZ mode. 266 */ 267 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 2; 268 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 4; 269 } 270 alpha_bus_get_window = cia_bus_get_window; 271 } 272 ccp->cc_mallocsafe = mallocsafe; 273 274 cia_pci_init(&ccp->cc_pc, ccp); 275 alpha_pci_chipset = &ccp->cc_pc; 276 277 ccp->cc_initted = 1; 278 } 279 280 void 281 ciaattach(parent, self, aux) 282 struct device *parent, *self; 283 void *aux; 284 { 285 struct cia_softc *sc = (struct cia_softc *)self; 286 struct cia_config *ccp; 287 struct pcibus_attach_args pba; 288 char bits[64]; 289 const char *name; 290 int pass; 291 292 /* note that we've attached the chipset; can't have 2 CIAs. */ 293 ciafound = 1; 294 295 /* 296 * set up the chipset's info; done once at console init time 297 * (maybe), but we must do it here as well to take care of things 298 * that need to use memory allocation. 299 */ 300 ccp = sc->sc_ccp = &cia_configuration; 301 cia_init(ccp, 1); 302 303 if (ccp->cc_flags & CCF_ISPYXIS) { 304 name = "Pyxis"; 305 pass = ccp->cc_rev; 306 } else { 307 name = "ALCOR/ALCOR2"; 308 pass = ccp->cc_rev + 1; 309 } 310 311 printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n", 312 name, pass); 313 if (ccp->cc_cnfg) 314 printf("%s: extended capabilities: %s\n", self->dv_xname, 315 bitmask_snprintf(ccp->cc_cnfg, CIA_CSR_CNFG_BITS, 316 bits, sizeof(bits))); 317 318 switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) { 319 case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX: 320 name = "PCI config and bus"; 321 break; 322 case CCF_PCI_USE_BWX: 323 name = "PCI config"; 324 break; 325 case CCF_BUS_USE_BWX: 326 name = "bus"; 327 break; 328 default: 329 name = NULL; 330 break; 331 } 332 if (name != NULL) 333 printf("%s: using BWX for %s access\n", self->dv_xname, name); 334 335 #ifdef DEC_550 336 if (cputype == ST_DEC_550 && 337 (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 338 /* 339 * Miata 1 systems have a bug: DMA cannot cross 340 * an 8k boundary! Make sure PCI read prefetching 341 * is disabled on these chips. Note that secondary 342 * PCI busses don't have this problem, because of 343 * the way PPBs handle PCI read requests. 344 * 345 * In the 21174 Technical Reference Manual, this is 346 * actually documented as "Pyxis Pass 1", but apparently 347 * there are chips that report themselves as "Pass 1" 348 * which do not have the bug! Miatas with the Cypress 349 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not 350 * have the bug, so we use this check. 351 * 352 * NOTE: This bug is actually worked around in cia_dma.c, 353 * when direct-mapped DMA maps are created. 354 * 355 * XXX WE NEED TO THINK ABOUT HOW TO HANDLE THIS FOR 356 * XXX SGMAP DMA MAPPINGS! 357 */ 358 u_int32_t ctrl; 359 360 /* XXX no bets... */ 361 printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n", 362 self->dv_xname); 363 364 ccp->cc_flags |= CCF_PYXISBUG; 365 366 alpha_mb(); 367 ctrl = REGVAL(CIA_CSR_CTRL); 368 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE); 369 REGVAL(CIA_CSR_CTRL) = ctrl; 370 alpha_mb(); 371 } 372 #endif /* DEC_550 */ 373 374 cia_dma_init(ccp); 375 376 switch (cputype) { 377 #ifdef DEC_KN20AA 378 case ST_DEC_KN20AA: 379 pci_kn20aa_pickintr(ccp); 380 break; 381 #endif 382 383 #ifdef DEC_EB164 384 case ST_EB164: 385 pci_eb164_pickintr(ccp); 386 break; 387 #endif 388 389 #ifdef DEC_550 390 case ST_DEC_550: 391 pci_550_pickintr(ccp); 392 break; 393 #endif 394 395 #ifdef DEC_1000A 396 case ST_DEC_1000A: 397 pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 398 &ccp->cc_pc); 399 break; 400 #endif 401 402 #ifdef DEC_1000 403 case ST_DEC_1000: 404 pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 405 &ccp->cc_pc); 406 break; 407 #endif 408 409 default: 410 panic("ciaattach: shouldn't be here, really..."); 411 } 412 413 pba.pba_busname = "pci"; 414 pba.pba_iot = &ccp->cc_iot; 415 pba.pba_memt = &ccp->cc_memt; 416 pba.pba_dmat = 417 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI); 418 pba.pba_dmat64 = NULL; 419 pba.pba_pc = &ccp->cc_pc; 420 pba.pba_bus = 0; 421 pba.pba_bridgetag = NULL; 422 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 423 if ((ccp->cc_flags & CCF_PYXISBUG) == 0) 424 pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | 425 PCI_FLAGS_MWI_OKAY; 426 config_found(self, &pba, ciaprint); 427 } 428 429 static int 430 ciaprint(aux, pnp) 431 void *aux; 432 const char *pnp; 433 { 434 register struct pcibus_attach_args *pba = aux; 435 436 /* only PCIs can attach to CIAs; easy. */ 437 if (pnp) 438 aprint_normal("%s at %s", pba->pba_busname, pnp); 439 aprint_normal(" bus %d", pba->pba_bus); 440 return (UNCONF); 441 } 442 443 int 444 cia_bus_get_window(type, window, abst) 445 int type, window; 446 struct alpha_bus_space_translation *abst; 447 { 448 struct cia_config *ccp = &cia_configuration; 449 bus_space_tag_t st; 450 451 switch (type) { 452 case ALPHA_BUS_TYPE_PCI_IO: 453 st = &ccp->cc_iot; 454 break; 455 456 case ALPHA_BUS_TYPE_PCI_MEM: 457 st = &ccp->cc_memt; 458 break; 459 460 default: 461 panic("cia_bus_get_window"); 462 } 463 464 return (alpha_bus_space_get_window(st, window, abst)); 465 } 466 467 void 468 cia_pyxis_intr_enable(irq, onoff) 469 int irq, onoff; 470 { 471 u_int64_t imask; 472 int s; 473 474 #if 0 475 printf("cia_pyxis_intr_enable: %s %d\n", 476 onoff ? "enabling" : "disabling", irq); 477 #endif 478 479 s = splhigh(); 480 alpha_mb(); 481 imask = REGVAL64(PYXIS_INT_MASK); 482 if (onoff) 483 imask |= (1UL << irq); 484 else 485 imask &= ~(1UL << irq); 486 REGVAL64(PYXIS_INT_MASK) = imask; 487 alpha_mb(); 488 splx(s); 489 } 490
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