cia.c revision 1.63
1 /* $NetBSD: cia.c,v 1.63 2004/08/30 15:05:15 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_eb164.h" 68 #include "opt_dec_kn20aa.h" 69 #include "opt_dec_550.h" 70 #include "opt_dec_1000a.h" 71 #include "opt_dec_1000.h" 72 73 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 74 75 __KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.63 2004/08/30 15:05:15 drochner Exp $"); 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/kernel.h> 80 #include <sys/malloc.h> 81 #include <sys/device.h> 82 83 #include <uvm/uvm_extern.h> 84 85 #include <machine/autoconf.h> 86 #include <machine/rpb.h> 87 #include <machine/sysarch.h> 88 #include <machine/alpha.h> 89 90 #include <dev/isa/isareg.h> 91 #include <dev/isa/isavar.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 #include <alpha/pci/ciareg.h> 96 #include <alpha/pci/ciavar.h> 97 98 #ifdef DEC_KN20AA 99 #include <alpha/pci/pci_kn20aa.h> 100 #endif 101 #ifdef DEC_EB164 102 #include <alpha/pci/pci_eb164.h> 103 #endif 104 #ifdef DEC_550 105 #include <alpha/pci/pci_550.h> 106 #endif 107 #ifdef DEC_1000A 108 #include <alpha/pci/pci_1000a.h> 109 #endif 110 #ifdef DEC_1000 111 #include <alpha/pci/pci_1000.h> 112 #endif 113 114 int ciamatch __P((struct device *, struct cfdata *, void *)); 115 void ciaattach __P((struct device *, struct device *, void *)); 116 117 CFATTACH_DECL(cia, sizeof(struct cia_softc), 118 ciamatch, ciaattach, NULL, NULL); 119 120 extern struct cfdriver cia_cd; 121 122 int cia_bus_get_window __P((int, int, 123 struct alpha_bus_space_translation *)); 124 125 /* There can be only one. */ 126 int ciafound; 127 struct cia_config cia_configuration; 128 129 /* 130 * This determines if we attempt to use BWX for PCI bus and config space 131 * access. Some systems, notably with Pyxis, don't fare so well unless 132 * BWX is used. 133 * 134 * EXCEPT! Some devices have a really hard time if BWX is used (WHY?!). 135 * So, we decouple the uses for PCI config space and PCI bus space. 136 * 137 * FURTHERMORE! The Pyxis, most notably earlier revs, really don't 138 * do so well if you don't use BWX for bus access. So we default to 139 * forcing BWX on those chips. 140 * 141 * Geez. 142 */ 143 144 #ifndef CIA_PCI_USE_BWX 145 #define CIA_PCI_USE_BWX 1 146 #endif 147 148 #ifndef CIA_BUS_USE_BWX 149 #define CIA_BUS_USE_BWX 0 150 #endif 151 152 #ifndef CIA_PYXIS_FORCE_BWX 153 #define CIA_PYXIS_FORCE_BWX 0 154 #endif 155 156 int cia_pci_use_bwx = CIA_PCI_USE_BWX; 157 int cia_bus_use_bwx = CIA_BUS_USE_BWX; 158 int cia_pyxis_force_bwx = CIA_PYXIS_FORCE_BWX; 159 160 int 161 ciamatch(parent, match, aux) 162 struct device *parent; 163 struct cfdata *match; 164 void *aux; 165 { 166 struct mainbus_attach_args *ma = aux; 167 168 /* Make sure that we're looking for a CIA. */ 169 if (strcmp(ma->ma_name, cia_cd.cd_name) != 0) 170 return (0); 171 172 if (ciafound) 173 return (0); 174 175 return (1); 176 } 177 178 /* 179 * Set up the chipset's function pointers. 180 */ 181 void 182 cia_init(ccp, mallocsafe) 183 struct cia_config *ccp; 184 int mallocsafe; 185 { 186 int pci_use_bwx = cia_pci_use_bwx; 187 int bus_use_bwx = cia_bus_use_bwx; 188 189 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM); 190 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO); 191 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK; 192 193 /* 194 * Determine if we have a Pyxis. Only two systypes can 195 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX) 196 * and the DEC_550 systype (Miata). 197 */ 198 if ((cputype == ST_EB164 && 199 (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) || 200 cputype == ST_DEC_550) { 201 ccp->cc_flags |= CCF_ISPYXIS; 202 if (cia_pyxis_force_bwx) 203 pci_use_bwx = bus_use_bwx = 1; 204 } 205 206 /* 207 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register. 208 */ 209 if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0) 210 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG); 211 else 212 ccp->cc_cnfg = 0; 213 214 /* 215 * Use BWX iff: 216 * 217 * - It hasn't been disbled by the user, 218 * - it's enabled in CNFG, 219 * - we're implementation version ev5, 220 * - BWX is enabled in the CPU's capabilities mask 221 */ 222 if ((pci_use_bwx || bus_use_bwx) && 223 (ccp->cc_cnfg & CNFG_BWEN) != 0 && 224 (cpu_amask & ALPHA_AMASK_BWX) != 0) { 225 u_int32_t ctrl; 226 227 if (pci_use_bwx) 228 ccp->cc_flags |= CCF_PCI_USE_BWX; 229 if (bus_use_bwx) 230 ccp->cc_flags |= CCF_BUS_USE_BWX; 231 232 /* 233 * For whatever reason, the firmware seems to enable PCI 234 * loopback mode if it also enables BWX. Make sure it's 235 * enabled if we have an old, buggy firmware rev. 236 */ 237 alpha_mb(); 238 ctrl = REGVAL(CIA_CSR_CTRL); 239 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) { 240 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 241 alpha_mb(); 242 } 243 } 244 245 if (!ccp->cc_initted) { 246 /* don't do these twice since they set up extents */ 247 if (ccp->cc_flags & CCF_BUS_USE_BWX) { 248 cia_bwx_bus_io_init(&ccp->cc_iot, ccp); 249 cia_bwx_bus_mem_init(&ccp->cc_memt, ccp); 250 251 /* 252 * We have one window for both PCI I/O and MEM 253 * in BWX mode. 254 */ 255 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1; 256 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1; 257 } else { 258 cia_swiz_bus_io_init(&ccp->cc_iot, ccp); 259 cia_swiz_bus_mem_init(&ccp->cc_memt, ccp); 260 261 /* 262 * We have two I/O windows and 4 MEM windows in 263 * SWIZ mode. 264 */ 265 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 2; 266 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 4; 267 } 268 alpha_bus_get_window = cia_bus_get_window; 269 } 270 ccp->cc_mallocsafe = mallocsafe; 271 272 cia_pci_init(&ccp->cc_pc, ccp); 273 alpha_pci_chipset = &ccp->cc_pc; 274 275 ccp->cc_initted = 1; 276 } 277 278 void 279 ciaattach(parent, self, aux) 280 struct device *parent, *self; 281 void *aux; 282 { 283 struct cia_softc *sc = (struct cia_softc *)self; 284 struct cia_config *ccp; 285 struct pcibus_attach_args pba; 286 char bits[64]; 287 const char *name; 288 int pass; 289 290 /* note that we've attached the chipset; can't have 2 CIAs. */ 291 ciafound = 1; 292 293 /* 294 * set up the chipset's info; done once at console init time 295 * (maybe), but we must do it here as well to take care of things 296 * that need to use memory allocation. 297 */ 298 ccp = sc->sc_ccp = &cia_configuration; 299 cia_init(ccp, 1); 300 301 if (ccp->cc_flags & CCF_ISPYXIS) { 302 name = "Pyxis"; 303 pass = ccp->cc_rev; 304 } else { 305 name = "ALCOR/ALCOR2"; 306 pass = ccp->cc_rev + 1; 307 } 308 309 printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n", 310 name, pass); 311 if (ccp->cc_cnfg) 312 printf("%s: extended capabilities: %s\n", self->dv_xname, 313 bitmask_snprintf(ccp->cc_cnfg, CIA_CSR_CNFG_BITS, 314 bits, sizeof(bits))); 315 316 switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) { 317 case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX: 318 name = "PCI config and bus"; 319 break; 320 case CCF_PCI_USE_BWX: 321 name = "PCI config"; 322 break; 323 case CCF_BUS_USE_BWX: 324 name = "bus"; 325 break; 326 default: 327 name = NULL; 328 break; 329 } 330 if (name != NULL) 331 printf("%s: using BWX for %s access\n", self->dv_xname, name); 332 333 #ifdef DEC_550 334 if (cputype == ST_DEC_550 && 335 (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 336 /* 337 * Miata 1 systems have a bug: DMA cannot cross 338 * an 8k boundary! Make sure PCI read prefetching 339 * is disabled on these chips. Note that secondary 340 * PCI busses don't have this problem, because of 341 * the way PPBs handle PCI read requests. 342 * 343 * In the 21174 Technical Reference Manual, this is 344 * actually documented as "Pyxis Pass 1", but apparently 345 * there are chips that report themselves as "Pass 1" 346 * which do not have the bug! Miatas with the Cypress 347 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not 348 * have the bug, so we use this check. 349 * 350 * NOTE: This bug is actually worked around in cia_dma.c, 351 * when direct-mapped DMA maps are created. 352 * 353 * XXX WE NEED TO THINK ABOUT HOW TO HANDLE THIS FOR 354 * XXX SGMAP DMA MAPPINGS! 355 */ 356 u_int32_t ctrl; 357 358 /* XXX no bets... */ 359 printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n", 360 self->dv_xname); 361 362 ccp->cc_flags |= CCF_PYXISBUG; 363 364 alpha_mb(); 365 ctrl = REGVAL(CIA_CSR_CTRL); 366 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE); 367 REGVAL(CIA_CSR_CTRL) = ctrl; 368 alpha_mb(); 369 } 370 #endif /* DEC_550 */ 371 372 cia_dma_init(ccp); 373 374 switch (cputype) { 375 #ifdef DEC_KN20AA 376 case ST_DEC_KN20AA: 377 pci_kn20aa_pickintr(ccp); 378 break; 379 #endif 380 381 #ifdef DEC_EB164 382 case ST_EB164: 383 pci_eb164_pickintr(ccp); 384 break; 385 #endif 386 387 #ifdef DEC_550 388 case ST_DEC_550: 389 pci_550_pickintr(ccp); 390 break; 391 #endif 392 393 #ifdef DEC_1000A 394 case ST_DEC_1000A: 395 pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 396 &ccp->cc_pc); 397 break; 398 #endif 399 400 #ifdef DEC_1000 401 case ST_DEC_1000: 402 pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 403 &ccp->cc_pc); 404 break; 405 #endif 406 407 default: 408 panic("ciaattach: shouldn't be here, really..."); 409 } 410 411 pba.pba_iot = &ccp->cc_iot; 412 pba.pba_memt = &ccp->cc_memt; 413 pba.pba_dmat = 414 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI); 415 pba.pba_dmat64 = NULL; 416 pba.pba_pc = &ccp->cc_pc; 417 pba.pba_bus = 0; 418 pba.pba_bridgetag = NULL; 419 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 420 if ((ccp->cc_flags & CCF_PYXISBUG) == 0) 421 pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | 422 PCI_FLAGS_MWI_OKAY; 423 config_found_ia(self, "pcibus", &pba, pcibusprint); 424 } 425 426 int 427 cia_bus_get_window(type, window, abst) 428 int type, window; 429 struct alpha_bus_space_translation *abst; 430 { 431 struct cia_config *ccp = &cia_configuration; 432 bus_space_tag_t st; 433 434 switch (type) { 435 case ALPHA_BUS_TYPE_PCI_IO: 436 st = &ccp->cc_iot; 437 break; 438 439 case ALPHA_BUS_TYPE_PCI_MEM: 440 st = &ccp->cc_memt; 441 break; 442 443 default: 444 panic("cia_bus_get_window"); 445 } 446 447 return (alpha_bus_space_get_window(st, window, abst)); 448 } 449 450 void 451 cia_pyxis_intr_enable(irq, onoff) 452 int irq, onoff; 453 { 454 u_int64_t imask; 455 int s; 456 457 #if 0 458 printf("cia_pyxis_intr_enable: %s %d\n", 459 onoff ? "enabling" : "disabling", irq); 460 #endif 461 462 s = splhigh(); 463 alpha_mb(); 464 imask = REGVAL64(PYXIS_INT_MASK); 465 if (onoff) 466 imask |= (1UL << irq); 467 else 468 imask &= ~(1UL << irq); 469 REGVAL64(PYXIS_INT_MASK) = imask; 470 alpha_mb(); 471 splx(s); 472 } 473
Indexes created Wed Oct 01 19:09:53 GMT 2025