cia.c revision 1.67
1 /* $NetBSD: cia.c,v 1.67 2009/03/14 14:45:53 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include "opt_dec_eb164.h" 61 #include "opt_dec_kn20aa.h" 62 #include "opt_dec_550.h" 63 #include "opt_dec_1000a.h" 64 #include "opt_dec_1000.h" 65 66 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 67 68 __KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.67 2009/03/14 14:45:53 dsl Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/malloc.h> 74 #include <sys/device.h> 75 76 #include <uvm/uvm_extern.h> 77 78 #include <machine/autoconf.h> 79 #include <machine/rpb.h> 80 #include <machine/sysarch.h> 81 #include <machine/alpha.h> 82 83 #include <dev/isa/isareg.h> 84 #include <dev/isa/isavar.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <alpha/pci/ciareg.h> 89 #include <alpha/pci/ciavar.h> 90 91 #ifdef DEC_KN20AA 92 #include <alpha/pci/pci_kn20aa.h> 93 #endif 94 #ifdef DEC_EB164 95 #include <alpha/pci/pci_eb164.h> 96 #endif 97 #ifdef DEC_550 98 #include <alpha/pci/pci_550.h> 99 #endif 100 #ifdef DEC_1000A 101 #include <alpha/pci/pci_1000a.h> 102 #endif 103 #ifdef DEC_1000 104 #include <alpha/pci/pci_1000.h> 105 #endif 106 107 int ciamatch(struct device *, struct cfdata *, void *); 108 void ciaattach(struct device *, struct device *, void *); 109 110 CFATTACH_DECL(cia, sizeof(struct cia_softc), 111 ciamatch, ciaattach, NULL, NULL); 112 113 extern struct cfdriver cia_cd; 114 115 int cia_bus_get_window(int, int, 116 struct alpha_bus_space_translation *); 117 118 /* There can be only one. */ 119 int ciafound; 120 struct cia_config cia_configuration; 121 122 /* 123 * This determines if we attempt to use BWX for PCI bus and config space 124 * access. Some systems, notably with Pyxis, don't fare so well unless 125 * BWX is used. 126 * 127 * EXCEPT! Some devices have a really hard time if BWX is used (WHY?!). 128 * So, we decouple the uses for PCI config space and PCI bus space. 129 * 130 * FURTHERMORE! The Pyxis, most notably earlier revs, really don't 131 * do so well if you don't use BWX for bus access. So we default to 132 * forcing BWX on those chips. 133 * 134 * Geez. 135 */ 136 137 #ifndef CIA_PCI_USE_BWX 138 #define CIA_PCI_USE_BWX 1 139 #endif 140 141 #ifndef CIA_BUS_USE_BWX 142 #define CIA_BUS_USE_BWX 0 143 #endif 144 145 #ifndef CIA_PYXIS_FORCE_BWX 146 #define CIA_PYXIS_FORCE_BWX 0 147 #endif 148 149 int cia_pci_use_bwx = CIA_PCI_USE_BWX; 150 int cia_bus_use_bwx = CIA_BUS_USE_BWX; 151 int cia_pyxis_force_bwx = CIA_PYXIS_FORCE_BWX; 152 153 int 154 ciamatch(parent, match, aux) 155 struct device *parent; 156 struct cfdata *match; 157 void *aux; 158 { 159 struct mainbus_attach_args *ma = aux; 160 161 /* Make sure that we're looking for a CIA. */ 162 if (strcmp(ma->ma_name, cia_cd.cd_name) != 0) 163 return (0); 164 165 if (ciafound) 166 return (0); 167 168 return (1); 169 } 170 171 /* 172 * Set up the chipset's function pointers. 173 */ 174 void 175 cia_init(ccp, mallocsafe) 176 struct cia_config *ccp; 177 int mallocsafe; 178 { 179 int pci_use_bwx = cia_pci_use_bwx; 180 int bus_use_bwx = cia_bus_use_bwx; 181 182 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM); 183 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO); 184 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK; 185 186 /* 187 * Determine if we have a Pyxis. Only two systypes can 188 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX) 189 * and the DEC_550 systype (Miata). 190 */ 191 if ((cputype == ST_EB164 && 192 (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) || 193 cputype == ST_DEC_550) { 194 ccp->cc_flags |= CCF_ISPYXIS; 195 if (cia_pyxis_force_bwx) 196 pci_use_bwx = bus_use_bwx = 1; 197 } 198 199 /* 200 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register. 201 */ 202 if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0) 203 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG); 204 else 205 ccp->cc_cnfg = 0; 206 207 /* 208 * Use BWX iff: 209 * 210 * - It hasn't been disbled by the user, 211 * - it's enabled in CNFG, 212 * - we're implementation version ev5, 213 * - BWX is enabled in the CPU's capabilities mask 214 */ 215 if ((pci_use_bwx || bus_use_bwx) && 216 (ccp->cc_cnfg & CNFG_BWEN) != 0 && 217 (cpu_amask & ALPHA_AMASK_BWX) != 0) { 218 u_int32_t ctrl; 219 220 if (pci_use_bwx) 221 ccp->cc_flags |= CCF_PCI_USE_BWX; 222 if (bus_use_bwx) 223 ccp->cc_flags |= CCF_BUS_USE_BWX; 224 225 /* 226 * For whatever reason, the firmware seems to enable PCI 227 * loopback mode if it also enables BWX. Make sure it's 228 * enabled if we have an old, buggy firmware rev. 229 */ 230 alpha_mb(); 231 ctrl = REGVAL(CIA_CSR_CTRL); 232 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) { 233 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 234 alpha_mb(); 235 } 236 } 237 238 if (!ccp->cc_initted) { 239 /* don't do these twice since they set up extents */ 240 if (ccp->cc_flags & CCF_BUS_USE_BWX) { 241 cia_bwx_bus_io_init(&ccp->cc_iot, ccp); 242 cia_bwx_bus_mem_init(&ccp->cc_memt, ccp); 243 244 /* 245 * We have one window for both PCI I/O and MEM 246 * in BWX mode. 247 */ 248 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1; 249 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1; 250 } else { 251 cia_swiz_bus_io_init(&ccp->cc_iot, ccp); 252 cia_swiz_bus_mem_init(&ccp->cc_memt, ccp); 253 254 /* 255 * We have two I/O windows and 4 MEM windows in 256 * SWIZ mode. 257 */ 258 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 2; 259 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 4; 260 } 261 alpha_bus_get_window = cia_bus_get_window; 262 } 263 ccp->cc_mallocsafe = mallocsafe; 264 265 cia_pci_init(&ccp->cc_pc, ccp); 266 alpha_pci_chipset = &ccp->cc_pc; 267 268 ccp->cc_initted = 1; 269 } 270 271 void 272 ciaattach(parent, self, aux) 273 struct device *parent, *self; 274 void *aux; 275 { 276 struct cia_softc *sc = (struct cia_softc *)self; 277 struct cia_config *ccp; 278 struct pcibus_attach_args pba; 279 char bits[64]; 280 const char *name; 281 int pass; 282 283 /* note that we've attached the chipset; can't have 2 CIAs. */ 284 ciafound = 1; 285 286 /* 287 * set up the chipset's info; done once at console init time 288 * (maybe), but we must do it here as well to take care of things 289 * that need to use memory allocation. 290 */ 291 ccp = sc->sc_ccp = &cia_configuration; 292 cia_init(ccp, 1); 293 294 if (ccp->cc_flags & CCF_ISPYXIS) { 295 name = "Pyxis"; 296 pass = ccp->cc_rev; 297 } else { 298 name = "ALCOR/ALCOR2"; 299 pass = ccp->cc_rev + 1; 300 } 301 302 printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n", 303 name, pass); 304 if (ccp->cc_cnfg) { 305 snprintb(bits, sizeof(bits), CIA_CSR_CNFG_BITS, ccp->cc_cnfg); 306 printf("%s: extended capabilities: %s\n", self->dv_xname, bits); 307 } 308 309 switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) { 310 case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX: 311 name = "PCI config and bus"; 312 break; 313 case CCF_PCI_USE_BWX: 314 name = "PCI config"; 315 break; 316 case CCF_BUS_USE_BWX: 317 name = "bus"; 318 break; 319 default: 320 name = NULL; 321 break; 322 } 323 if (name != NULL) 324 printf("%s: using BWX for %s access\n", self->dv_xname, name); 325 326 #ifdef DEC_550 327 if (cputype == ST_DEC_550 && 328 (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 329 /* 330 * Miata 1 systems have a bug: DMA cannot cross 331 * an 8k boundary! Make sure PCI read prefetching 332 * is disabled on these chips. Note that secondary 333 * PCI busses don't have this problem, because of 334 * the way PPBs handle PCI read requests. 335 * 336 * In the 21174 Technical Reference Manual, this is 337 * actually documented as "Pyxis Pass 1", but apparently 338 * there are chips that report themselves as "Pass 1" 339 * which do not have the bug! Miatas with the Cypress 340 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not 341 * have the bug, so we use this check. 342 * 343 * NOTE: This bug is actually worked around in cia_dma.c, 344 * when direct-mapped DMA maps are created. 345 * 346 * XXX WE NEED TO THINK ABOUT HOW TO HANDLE THIS FOR 347 * XXX SGMAP DMA MAPPINGS! 348 */ 349 u_int32_t ctrl; 350 351 /* XXX no bets... */ 352 printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n", 353 self->dv_xname); 354 355 ccp->cc_flags |= CCF_PYXISBUG; 356 357 alpha_mb(); 358 ctrl = REGVAL(CIA_CSR_CTRL); 359 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE); 360 REGVAL(CIA_CSR_CTRL) = ctrl; 361 alpha_mb(); 362 } 363 #endif /* DEC_550 */ 364 365 cia_dma_init(ccp); 366 367 switch (cputype) { 368 #ifdef DEC_KN20AA 369 case ST_DEC_KN20AA: 370 pci_kn20aa_pickintr(ccp); 371 break; 372 #endif 373 374 #ifdef DEC_EB164 375 case ST_EB164: 376 pci_eb164_pickintr(ccp); 377 break; 378 #endif 379 380 #ifdef DEC_550 381 case ST_DEC_550: 382 pci_550_pickintr(ccp); 383 break; 384 #endif 385 386 #ifdef DEC_1000A 387 case ST_DEC_1000A: 388 pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 389 &ccp->cc_pc); 390 break; 391 #endif 392 393 #ifdef DEC_1000 394 case ST_DEC_1000: 395 pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt, 396 &ccp->cc_pc); 397 break; 398 #endif 399 400 default: 401 panic("ciaattach: shouldn't be here, really..."); 402 } 403 404 pba.pba_iot = &ccp->cc_iot; 405 pba.pba_memt = &ccp->cc_memt; 406 pba.pba_dmat = 407 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI); 408 pba.pba_dmat64 = NULL; 409 pba.pba_pc = &ccp->cc_pc; 410 pba.pba_bus = 0; 411 pba.pba_bridgetag = NULL; 412 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 413 if ((ccp->cc_flags & CCF_PYXISBUG) == 0) 414 pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | 415 PCI_FLAGS_MWI_OKAY; 416 config_found_ia(self, "pcibus", &pba, pcibusprint); 417 } 418 419 int 420 cia_bus_get_window(type, window, abst) 421 int type, window; 422 struct alpha_bus_space_translation *abst; 423 { 424 struct cia_config *ccp = &cia_configuration; 425 bus_space_tag_t st; 426 427 switch (type) { 428 case ALPHA_BUS_TYPE_PCI_IO: 429 st = &ccp->cc_iot; 430 break; 431 432 case ALPHA_BUS_TYPE_PCI_MEM: 433 st = &ccp->cc_memt; 434 break; 435 436 default: 437 panic("cia_bus_get_window"); 438 } 439 440 return (alpha_bus_space_get_window(st, window, abst)); 441 } 442 443 void 444 cia_pyxis_intr_enable(irq, onoff) 445 int irq, onoff; 446 { 447 u_int64_t imask; 448 int s; 449 450 #if 0 451 printf("cia_pyxis_intr_enable: %s %d\n", 452 onoff ? "enabling" : "disabling", irq); 453 #endif 454 455 s = splhigh(); 456 alpha_mb(); 457 imask = REGVAL64(PYXIS_INT_MASK); 458 if (onoff) 459 imask |= (1UL << irq); 460 else 461 imask &= ~(1UL << irq); 462 REGVAL64(PYXIS_INT_MASK) = imask; 463 alpha_mb(); 464 splx(s); 465 } 466
Indexes created Tue Sep 30 11:09:46 GMT 2025