cia_dma.c revision 1.23
1 /* $NetBSD: cia_dma.c,v 1.23 2009/03/14 14:45:53 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: cia_dma.c,v 1.23 2009/03/14 14:45:53 dsl Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #define _ALPHA_BUS_DMA_PRIVATE 46 #include <machine/bus.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <alpha/pci/ciareg.h> 51 #include <alpha/pci/ciavar.h> 52 53 bus_dma_tag_t cia_dma_get_tag(bus_dma_tag_t, alpha_bus_t); 54 55 int cia_bus_dmamap_create_direct(bus_dma_tag_t, bus_size_t, int, 56 bus_size_t, bus_size_t, int, bus_dmamap_t *); 57 58 int cia_bus_dmamap_load_sgmap(bus_dma_tag_t, bus_dmamap_t, void *, 59 bus_size_t, struct proc *, int); 60 61 int cia_bus_dmamap_load_mbuf_sgmap(bus_dma_tag_t, bus_dmamap_t, 62 struct mbuf *, int); 63 64 int cia_bus_dmamap_load_uio_sgmap(bus_dma_tag_t, bus_dmamap_t, 65 struct uio *, int); 66 67 int cia_bus_dmamap_load_raw_sgmap(bus_dma_tag_t, bus_dmamap_t, 68 bus_dma_segment_t *, int, bus_size_t, int); 69 70 void cia_bus_dmamap_unload_sgmap(bus_dma_tag_t, bus_dmamap_t); 71 72 /* 73 * Direct-mapped window: 1G at 1G 74 */ 75 #define CIA_DIRECT_MAPPED_BASE (1*1024*1024*1024) 76 #define CIA_DIRECT_MAPPED_SIZE (1*1024*1024*1024) 77 78 /* 79 * SGMAP window: 8M at 8M 80 */ 81 #define CIA_SGMAP_MAPPED_BASE (8*1024*1024) 82 #define CIA_SGMAP_MAPPED_SIZE (8*1024*1024) 83 84 /* ALCOR/ALGOR2/PYXIS have a 256-byte out-bound DMA prefetch threshold. */ 85 #define CIA_SGMAP_PFTHRESH 256 86 87 void cia_tlb_invalidate(void); 88 void cia_broken_pyxis_tlb_invalidate(void); 89 90 void (*cia_tlb_invalidate_fn)(void); 91 92 #define CIA_TLB_INVALIDATE() (*cia_tlb_invalidate_fn)() 93 94 struct alpha_sgmap cia_pyxis_bug_sgmap; 95 #define CIA_PYXIS_BUG_BASE (128*1024*1024) 96 #define CIA_PYXIS_BUG_SIZE (2*1024*1024) 97 98 void 99 cia_dma_init(ccp) 100 struct cia_config *ccp; 101 { 102 bus_addr_t tbase; 103 bus_dma_tag_t t; 104 105 /* 106 * Initialize the DMA tag used for direct-mapped DMA. 107 */ 108 t = &ccp->cc_dmat_direct; 109 t->_cookie = ccp; 110 t->_wbase = CIA_DIRECT_MAPPED_BASE; 111 t->_wsize = CIA_DIRECT_MAPPED_SIZE; 112 t->_next_window = &ccp->cc_dmat_sgmap; 113 t->_boundary = 0; 114 t->_sgmap = NULL; 115 t->_get_tag = cia_dma_get_tag; 116 t->_dmamap_create = cia_bus_dmamap_create_direct; 117 t->_dmamap_destroy = _bus_dmamap_destroy; 118 t->_dmamap_load = _bus_dmamap_load_direct; 119 t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct; 120 t->_dmamap_load_uio = _bus_dmamap_load_uio_direct; 121 t->_dmamap_load_raw = _bus_dmamap_load_raw_direct; 122 t->_dmamap_unload = _bus_dmamap_unload; 123 t->_dmamap_sync = _bus_dmamap_sync; 124 125 t->_dmamem_alloc = _bus_dmamem_alloc; 126 t->_dmamem_free = _bus_dmamem_free; 127 t->_dmamem_map = _bus_dmamem_map; 128 t->_dmamem_unmap = _bus_dmamem_unmap; 129 t->_dmamem_mmap = _bus_dmamem_mmap; 130 131 /* 132 * Initialize the DMA tag used for sgmap-mapped DMA. 133 */ 134 t = &ccp->cc_dmat_sgmap; 135 t->_cookie = ccp; 136 t->_wbase = CIA_SGMAP_MAPPED_BASE; 137 t->_wsize = CIA_SGMAP_MAPPED_SIZE; 138 t->_next_window = NULL; 139 t->_boundary = 0; 140 t->_sgmap = &ccp->cc_sgmap; 141 t->_pfthresh = CIA_SGMAP_PFTHRESH; 142 t->_get_tag = cia_dma_get_tag; 143 t->_dmamap_create = alpha_sgmap_dmamap_create; 144 t->_dmamap_destroy = alpha_sgmap_dmamap_destroy; 145 t->_dmamap_load = cia_bus_dmamap_load_sgmap; 146 t->_dmamap_load_mbuf = cia_bus_dmamap_load_mbuf_sgmap; 147 t->_dmamap_load_uio = cia_bus_dmamap_load_uio_sgmap; 148 t->_dmamap_load_raw = cia_bus_dmamap_load_raw_sgmap; 149 t->_dmamap_unload = cia_bus_dmamap_unload_sgmap; 150 t->_dmamap_sync = _bus_dmamap_sync; 151 152 t->_dmamem_alloc = _bus_dmamem_alloc; 153 t->_dmamem_free = _bus_dmamem_free; 154 t->_dmamem_map = _bus_dmamem_map; 155 t->_dmamem_unmap = _bus_dmamem_unmap; 156 t->_dmamem_mmap = _bus_dmamem_mmap; 157 158 /* 159 * The firmware has set up window 1 as a 1G direct-mapped DMA 160 * window beginning at 1G. We leave it alone. Leave window 161 * 0 alone until we reconfigure it for SGMAP-mapped DMA. 162 * Windows 2 and 3 are already disabled. 163 */ 164 165 /* 166 * Initialize the SGMAP. Must align page table to 32k 167 * (hardware bug?). 168 */ 169 alpha_sgmap_init(t, &ccp->cc_sgmap, "cia_sgmap", 170 CIA_SGMAP_MAPPED_BASE, 0, CIA_SGMAP_MAPPED_SIZE, 171 sizeof(u_int64_t), NULL, (32*1024)); 172 173 /* 174 * Set up window 0 as an 8MB SGMAP-mapped window 175 * starting at 8MB. 176 */ 177 REGVAL(CIA_PCI_W0BASE) = CIA_SGMAP_MAPPED_BASE | 178 CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN; 179 alpha_mb(); 180 181 REGVAL(CIA_PCI_W0MASK) = CIA_PCI_WnMASK_8M; 182 alpha_mb(); 183 184 tbase = ccp->cc_sgmap.aps_ptpa >> CIA_PCI_TnBASE_SHIFT; 185 if ((tbase & CIA_PCI_TnBASE_MASK) != tbase) 186 panic("cia_dma_init: bad page table address"); 187 REGVAL(CIA_PCI_T0BASE) = tbase; 188 alpha_mb(); 189 190 /* 191 * Pass 1 and 2 (i.e. revision <= 1) of the Pyxis have a 192 * broken scatter/gather TLB; it cannot be invalidated. To 193 * work around this problem, we configure window 2 as an SG 194 * 2M window at 128M, which we use in DMA loopback mode to 195 * read a spill page. This works by causing TLB misses, 196 * causing the old entries to be purged to make room for 197 * the new entries coming in for the spill page. 198 */ 199 if ((ccp->cc_flags & CCF_ISPYXIS) != 0 && ccp->cc_rev <= 1) { 200 u_int64_t *page_table; 201 int i; 202 203 cia_tlb_invalidate_fn = 204 cia_broken_pyxis_tlb_invalidate; 205 206 alpha_sgmap_init(t, &cia_pyxis_bug_sgmap, 207 "pyxis_bug_sgmap", CIA_PYXIS_BUG_BASE, 0, 208 CIA_PYXIS_BUG_SIZE, sizeof(u_int64_t), NULL, 209 (32*1024)); 210 211 REGVAL(CIA_PCI_W2BASE) = CIA_PYXIS_BUG_BASE | 212 CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN; 213 alpha_mb(); 214 215 REGVAL(CIA_PCI_W2MASK) = CIA_PCI_WnMASK_2M; 216 alpha_mb(); 217 218 tbase = cia_pyxis_bug_sgmap.aps_ptpa >> 219 CIA_PCI_TnBASE_SHIFT; 220 if ((tbase & CIA_PCI_TnBASE_MASK) != tbase) 221 panic("cia_dma_init: bad page table address"); 222 REGVAL(CIA_PCI_T2BASE) = tbase; 223 alpha_mb(); 224 225 /* 226 * Initialize the page table to point at the spill 227 * page. Leave the last entry invalid. 228 */ 229 pci_sgmap_pte64_init_spill_page_pte(); 230 for (i = 0, page_table = cia_pyxis_bug_sgmap.aps_pt; 231 i < (CIA_PYXIS_BUG_SIZE / PAGE_SIZE) - 1; i++) { 232 page_table[i] = 233 pci_sgmap_pte64_prefetch_spill_page_pte; 234 } 235 alpha_mb(); 236 } else 237 cia_tlb_invalidate_fn = cia_tlb_invalidate; 238 239 CIA_TLB_INVALIDATE(); 240 241 /* XXX XXX BEGIN XXX XXX */ 242 { /* XXX */ 243 extern paddr_t alpha_XXX_dmamap_or; /* XXX */ 244 alpha_XXX_dmamap_or = CIA_DIRECT_MAPPED_BASE; /* XXX */ 245 } /* XXX */ 246 /* XXX XXX END XXX XXX */ 247 } 248 249 /* 250 * Return the bus dma tag to be used for the specified bus type. 251 * INTERNAL USE ONLY! 252 */ 253 bus_dma_tag_t 254 cia_dma_get_tag(t, bustype) 255 bus_dma_tag_t t; 256 alpha_bus_t bustype; 257 { 258 struct cia_config *ccp = t->_cookie; 259 260 switch (bustype) { 261 case ALPHA_BUS_PCI: 262 case ALPHA_BUS_EISA: 263 /* 264 * Systems with a CIA can only support 1G 265 * of memory, so we use the direct-mapped window 266 * on busses that have 32-bit DMA. 267 * 268 * Ahem: I have a PWS 500au with 1.5G of memory, and it 269 * had problems doing DMA because it was not falling back 270 * to using SGMAPs. I've fixed that and my PWS now works with 271 * 1.5G. There have been other reports about failures with 272 * more than 1.0G of memory. Michael Hitch 273 */ 274 return (&ccp->cc_dmat_direct); 275 276 case ALPHA_BUS_ISA: 277 /* 278 * ISA doesn't have enough address bits to use 279 * the direct-mapped DMA window, so we must use 280 * SGMAPs. 281 */ 282 return (&ccp->cc_dmat_sgmap); 283 284 default: 285 panic("cia_dma_get_tag: shouldn't be here, really..."); 286 } 287 } 288 289 /* 290 * Create a CIA direct-mapped DMA map. 291 */ 292 int 293 cia_bus_dmamap_create_direct(t, size, nsegments, maxsegsz, boundary, 294 flags, dmamp) 295 bus_dma_tag_t t; 296 bus_size_t size; 297 int nsegments; 298 bus_size_t maxsegsz; 299 bus_size_t boundary; 300 int flags; 301 bus_dmamap_t *dmamp; 302 { 303 struct cia_config *ccp = t->_cookie; 304 bus_dmamap_t map; 305 int error; 306 307 error = _bus_dmamap_create(t, size, nsegments, maxsegsz, 308 boundary, flags, dmamp); 309 if (error) 310 return (error); 311 312 map = *dmamp; 313 314 if ((ccp->cc_flags & CCF_PYXISBUG) != 0 && 315 map->_dm_segcnt > 1) { 316 /* 317 * We have a Pyxis with the DMA page crossing bug, make 318 * sure we don't coalesce adjacent DMA segments. 319 * 320 * NOTE: We can only do this if the max segment count 321 * is greater than 1. This is because many network 322 * drivers allocate large contiguous blocks of memory 323 * for control data structures, even though they won't 324 * do any single DMA that crosses a page coundary. 325 * -- thorpej (at) NetBSD.org, 2/5/2000 326 */ 327 map->_dm_flags |= DMAMAP_NO_COALESCE; 328 } 329 330 return (0); 331 } 332 333 /* 334 * Load a CIA SGMAP-mapped DMA map with a linear buffer. 335 */ 336 int 337 cia_bus_dmamap_load_sgmap(t, map, buf, buflen, p, flags) 338 bus_dma_tag_t t; 339 bus_dmamap_t map; 340 void *buf; 341 bus_size_t buflen; 342 struct proc *p; 343 int flags; 344 { 345 int error; 346 347 error = pci_sgmap_pte64_load(t, map, buf, buflen, p, flags, 348 t->_sgmap); 349 if (error == 0) 350 CIA_TLB_INVALIDATE(); 351 352 return (error); 353 } 354 355 /* 356 * Load a CIA SGMAP-mapped DMA map with an mbuf chain. 357 */ 358 int 359 cia_bus_dmamap_load_mbuf_sgmap(t, map, m, flags) 360 bus_dma_tag_t t; 361 bus_dmamap_t map; 362 struct mbuf *m; 363 int flags; 364 { 365 int error; 366 367 error = pci_sgmap_pte64_load_mbuf(t, map, m, flags, t->_sgmap); 368 if (error == 0) 369 CIA_TLB_INVALIDATE(); 370 371 return (error); 372 } 373 374 /* 375 * Load a CIA SGMAP-mapped DMA map with a uio. 376 */ 377 int 378 cia_bus_dmamap_load_uio_sgmap(t, map, uio, flags) 379 bus_dma_tag_t t; 380 bus_dmamap_t map; 381 struct uio *uio; 382 int flags; 383 { 384 int error; 385 386 error = pci_sgmap_pte64_load_uio(t, map, uio, flags, t->_sgmap); 387 if (error == 0) 388 CIA_TLB_INVALIDATE(); 389 390 return (error); 391 } 392 393 /* 394 * Load a CIA SGMAP-mapped DMA map with raw memory. 395 */ 396 int 397 cia_bus_dmamap_load_raw_sgmap(t, map, segs, nsegs, size, flags) 398 bus_dma_tag_t t; 399 bus_dmamap_t map; 400 bus_dma_segment_t *segs; 401 int nsegs; 402 bus_size_t size; 403 int flags; 404 { 405 int error; 406 407 error = pci_sgmap_pte64_load_raw(t, map, segs, nsegs, size, flags, 408 t->_sgmap); 409 if (error == 0) 410 CIA_TLB_INVALIDATE(); 411 412 return (error); 413 } 414 415 /* 416 * Unload a CIA DMA map. 417 */ 418 void 419 cia_bus_dmamap_unload_sgmap(t, map) 420 bus_dma_tag_t t; 421 bus_dmamap_t map; 422 { 423 424 /* 425 * Invalidate any SGMAP page table entries used by this 426 * mapping. 427 */ 428 pci_sgmap_pte64_unload(t, map, t->_sgmap); 429 CIA_TLB_INVALIDATE(); 430 431 /* 432 * Do the generic bits of the unload. 433 */ 434 _bus_dmamap_unload(t, map); 435 } 436 437 /* 438 * Flush the CIA scatter/gather TLB. 439 */ 440 void 441 cia_tlb_invalidate() 442 { 443 444 alpha_mb(); 445 REGVAL(CIA_PCI_TBIA) = CIA_PCI_TBIA_ALL; 446 alpha_mb(); 447 } 448 449 /* 450 * Flush the scatter/gather TLB on broken Pyxis chips. 451 */ 452 void 453 cia_broken_pyxis_tlb_invalidate() 454 { 455 volatile u_int64_t dummy; 456 u_int32_t ctrl; 457 int i, s; 458 459 s = splhigh(); 460 461 /* 462 * Put the Pyxis into PCI loopback mode. 463 */ 464 alpha_mb(); 465 ctrl = REGVAL(CIA_CSR_CTRL); 466 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN; 467 alpha_mb(); 468 469 /* 470 * Now, read from PCI dense memory space at offset 128M (our 471 * target window base), skipping 64k on each read. This forces 472 * S/G TLB misses. 473 * 474 * XXX Looks like the TLB entries are `not quite LRU'. We need 475 * XXX to read more times than there are actual tags! 476 */ 477 for (i = 0; i < CIA_TLB_NTAGS + 4; i++) { 478 dummy = *((volatile u_int64_t *) 479 ALPHA_PHYS_TO_K0SEG(CIA_PCI_DENSE + CIA_PYXIS_BUG_BASE + 480 (i * 65536))); 481 } 482 483 /* 484 * Restore normal PCI operation. 485 */ 486 alpha_mb(); 487 REGVAL(CIA_CSR_CTRL) = ctrl; 488 alpha_mb(); 489 490 splx(s); 491 } 492
Indexes created Wed Oct 01 07:09:59 GMT 2025