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cia_swiz_bus_io.c revision 1.5 
      1 /*	$NetBSD: cia_swiz_bus_io.c,v 1.5 1996/08/27 16:29:25 cgd Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 #include <sys/param.h>
     31 #include <sys/systm.h>
     32 #include <sys/malloc.h>
     33 #include <sys/syslog.h>
     34 #include <sys/device.h>
     35 #include <vm/vm.h>
     36 
     37 #include <machine/bus.h>
     38 
     39 #include <alpha/pci/ciareg.h>
     40 #include <alpha/pci/ciavar.h>
     41 
     42 #define	CHIP		cia
     43 
     44 /* IO region 1 */
     45 #define CHIP_IO_W1_START(v)						\
     46 	    HAE_IO_REG1_START(((struct cia_config *)(v))->cc_hae_io)
     47 #define CHIP_IO_W1_END(v)						\
     48 	    (CHIP_IO_W1_START(v) + HAE_IO_REG1_MASK)
     49 #define CHIP_IO_W1_BASE(v)						\
     50 	    CIA_PCI_SIO1
     51 #define CHIP_IO_W1_MASK(v)						\
     52 	    HAE_IO_REG1_MASK
     53 
     54 /* IO region 2 */
     55 #define CHIP_IO_W2_START(v)						\
     56 	    HAE_IO_REG2_START(((struct cia_config *)(v))->cc_hae_io)
     57 #define CHIP_IO_W2_END(v)						\
     58 	    (CHIP_IO_W2_START(v) + HAE_IO_REG2_MASK)
     59 #define CHIP_IO_W2_BASE(v)						\
     60 	    CIA_PCI_SIO2
     61 #define CHIP_IO_W2_MASK(v)						\
     62 	    HAE_IO_REG2_MASK
     63 
     64 #include "pcs_bus_io_common.c"
     65