11.20Sthorpej/* $NetBSD: cia_swiz_bus_mem.c,v 1.20 2023/12/04 00:32:10 thorpej Exp $ */ 21.2Scgd 31.2Scgd/* 41.2Scgd * Copyright (c) 1996 Carnegie-Mellon University. 51.2Scgd * All rights reserved. 61.2Scgd * 71.2Scgd * Author: Chris G. Demetriou 81.2Scgd * 91.2Scgd * Permission to use, copy, modify and distribute this software and 101.2Scgd * its documentation is hereby granted, provided that both the copyright 111.2Scgd * notice and this permission notice appear in all copies of the 121.2Scgd * software, derivative works or modified versions, and any portions 131.2Scgd * thereof, and that both notices appear in supporting documentation. 141.2Scgd * 151.2Scgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 161.2Scgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 171.2Scgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 181.2Scgd * 191.2Scgd * Carnegie Mellon requests users of this software to return to 201.2Scgd * 211.2Scgd * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 221.2Scgd * School of Computer Science 231.2Scgd * Carnegie Mellon University 241.2Scgd * Pittsburgh PA 15213-3890 251.2Scgd * 261.2Scgd * any improvements or extensions that they make and grant Carnegie the 271.2Scgd * rights to redistribute these changes. 281.2Scgd */ 291.9Scgd 301.10Scgd#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 311.10Scgd 321.20Sthorpej__KERNEL_RCSID(1, "$NetBSD: cia_swiz_bus_mem.c,v 1.20 2023/12/04 00:32:10 thorpej Exp $"); 331.1Scgd 341.1Scgd#include <sys/param.h> 351.5Scgd#include <sys/systm.h> 361.1Scgd#include <sys/syslog.h> 371.1Scgd#include <sys/device.h> 381.16Smrg 391.18Sdyoung#include <sys/bus.h> 401.1Scgd 411.1Scgd#include <alpha/pci/ciareg.h> 421.3Scgd#include <alpha/pci/ciavar.h> 431.1Scgd 441.12Scgd#define CHIP cia_swiz 451.3Scgd 461.20Sthorpej#define CHIP_D_MEM_ARENA(v) (((struct cia_config *)(v))->cc_d_mem_arena) 471.20Sthorpej#define CHIP_S_MEM_ARENA(v) (((struct cia_config *)(v))->cc_s_mem_arena) 481.7Scgd 491.4Scgd/* Dense region 1 */ 501.7Scgd#define CHIP_D_MEM_W1_BUS_START(v) 0x00000000UL 511.7Scgd#define CHIP_D_MEM_W1_BUS_END(v) 0xffffffffUL 521.7Scgd#define CHIP_D_MEM_W1_SYS_START(v) CIA_PCI_DENSE 531.7Scgd#define CHIP_D_MEM_W1_SYS_END(v) (CIA_PCI_DENSE + 0xffffffffUL) 541.3Scgd 551.3Scgd/* Sparse region 1 */ 561.7Scgd#define CHIP_S_MEM_W1_BUS_START(v) \ 571.3Scgd HAE_MEM_REG1_START(((struct cia_config *)(v))->cc_hae_mem) 581.7Scgd#define CHIP_S_MEM_W1_BUS_END(v) \ 591.7Scgd (CHIP_S_MEM_W1_BUS_START(v) + HAE_MEM_REG1_MASK) 601.7Scgd#define CHIP_S_MEM_W1_SYS_START(v) \ 611.3Scgd CIA_PCI_SMEM1 621.7Scgd#define CHIP_S_MEM_W1_SYS_END(v) \ 631.7Scgd (CIA_PCI_SMEM1 + ((HAE_MEM_REG1_MASK + 1) << 5) - 1) 641.3Scgd 651.3Scgd/* Sparse region 2 */ 661.7Scgd#define CHIP_S_MEM_W2_BUS_START(v) \ 671.3Scgd HAE_MEM_REG2_START(((struct cia_config *)(v))->cc_hae_mem) 681.7Scgd#define CHIP_S_MEM_W2_BUS_END(v) \ 691.7Scgd (CHIP_S_MEM_W2_BUS_START(v) + HAE_MEM_REG2_MASK) 701.7Scgd#define CHIP_S_MEM_W2_SYS_START(v) \ 711.3Scgd CIA_PCI_SMEM2 721.7Scgd#define CHIP_S_MEM_W2_SYS_END(v) \ 731.7Scgd (CIA_PCI_SMEM2 + ((HAE_MEM_REG2_MASK + 1) << 5) - 1) 741.3Scgd 751.3Scgd/* Sparse region 3 */ 761.7Scgd#define CHIP_S_MEM_W3_BUS_START(v) \ 771.3Scgd HAE_MEM_REG3_START(((struct cia_config *)(v))->cc_hae_mem) 781.7Scgd#define CHIP_S_MEM_W3_BUS_END(v) \ 791.7Scgd (CHIP_S_MEM_W3_BUS_START(v) + HAE_MEM_REG3_MASK) 801.7Scgd#define CHIP_S_MEM_W3_SYS_START(v) \ 811.3Scgd CIA_PCI_SMEM3 821.7Scgd#define CHIP_S_MEM_W3_SYS_END(v) \ 831.7Scgd (CIA_PCI_SMEM3 + ((HAE_MEM_REG3_MASK + 1) << 5) - 1) 841.1Scgd 851.14Sthorpej#include <alpha/pci/pci_swiz_bus_mem_chipdep.c> 86