cia_swiz_bus_mem.c revision 1.3 
1/*	$NetBSD: cia_swiz_bus_mem.c,v 1.3 1996/06/10 00:04:55 cgd Exp $	*/
2
3/*
4 * Copyright (c) 1996 Carnegie-Mellon University.
5 * All rights reserved.
6 *
7 * Author: Chris G. Demetriou
8 *
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
14 *
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 *
19 * Carnegie Mellon requests users of this software to return to
20 *
21 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
22 *  School of Computer Science
23 *  Carnegie Mellon University
24 *  Pittsburgh PA 15213-3890
25 *
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
28 */
29
30#include <sys/param.h>
31#include <sys/malloc.h>
32#include <sys/syslog.h>
33#include <sys/device.h>
34#include <vm/vm.h>
35
36#include <machine/bus.h>
37
38#include <alpha/pci/ciareg.h>
39#include <alpha/pci/ciavar.h>
40
41#define	CHIP		cia
42
43/* Dense memory */
44#define	CHIP_D_MEM_BASE(v)	CIA_PCI_DENSE
45#define	CHIP_D_MEM_MASK(v)	0xffffffff
46
47/* Sparse region 1 */
48#define	CHIP_S_MEM_W1_START(v)						\
49	    HAE_MEM_REG1_START(((struct cia_config *)(v))->cc_hae_mem)
50#define	CHIP_S_MEM_W1_END(v)						\
51	    (CHIP_S_MEM_W1_START(v) + HAE_MEM_REG1_MASK)
52#define	CHIP_S_MEM_W1_BASE(v)						\
53	    CIA_PCI_SMEM1
54#define	CHIP_S_MEM_W1_MASK(v)						\
55	    HAE_MEM_REG1_MASK
56
57/* Sparse region 2 */
58#define	CHIP_S_MEM_W2_START(v)						\
59	    HAE_MEM_REG2_START(((struct cia_config *)(v))->cc_hae_mem)
60#define	CHIP_S_MEM_W2_END(v)						\
61	    (CHIP_S_MEM_W2_START(v) + HAE_MEM_REG2_MASK)
62#define	CHIP_S_MEM_W2_BASE(v)						\
63	    CIA_PCI_SMEM2
64#define	CHIP_S_MEM_W2_MASK(v)						\
65	    HAE_MEM_REG2_MASK
66
67/* Sparse region 3 */
68#define	CHIP_S_MEM_W3_START(v)						\
69	    HAE_MEM_REG3_START(((struct cia_config *)(v))->cc_hae_mem)
70#define	CHIP_S_MEM_W3_END(v)						\
71	    (CHIP_S_MEM_W3_START(v) + HAE_MEM_REG3_MASK)
72#define	CHIP_S_MEM_W3_BASE(v)						\
73	    CIA_PCI_SMEM3
74#define	CHIP_S_MEM_W3_MASK(v)						\
75	    HAE_MEM_REG3_MASK
76
77#include "pcs_bus_mem_common.c"
78