cia_swiz_bus_mem.c revision 1.8 
1/* $NetBSD: cia_swiz_bus_mem.c,v 1.8 1997/04/07 05:19:35 cgd Exp $ */
2
3/*
4 * Copyright (c) 1996 Carnegie-Mellon University.
5 * All rights reserved.
6 *
7 * Author: Chris G. Demetriou
8 *
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
14 *
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 *
19 * Carnegie Mellon requests users of this software to return to
20 *
21 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
22 *  School of Computer Science
23 *  Carnegie Mellon University
24 *  Pittsburgh PA 15213-3890
25 *
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
28 */
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/malloc.h>
33#include <sys/syslog.h>
34#include <sys/device.h>
35#include <vm/vm.h>
36
37#include <machine/bus.h>
38
39#include <alpha/pci/ciareg.h>
40#include <alpha/pci/ciavar.h>
41
42#define	CHIP		cia
43
44#define	CHIP_EX_MALLOC_SAFE(v)	(((struct cia_config *)(v))->cc_mallocsafe)
45#define	CHIP_D_MEM_EXTENT(v)	(((struct cia_config *)(v))->cc_d_mem_ex)
46#define	CHIP_S_MEM_EXTENT(v)	(((struct cia_config *)(v))->cc_s_mem_ex)
47
48/* Dense region 1 */
49#define	CHIP_D_MEM_W1_BUS_START(v)	0x00000000UL
50#define	CHIP_D_MEM_W1_BUS_END(v)	0xffffffffUL
51#define	CHIP_D_MEM_W1_SYS_START(v)	CIA_PCI_DENSE
52#define	CHIP_D_MEM_W1_SYS_END(v)	(CIA_PCI_DENSE + 0xffffffffUL)
53
54/* Sparse region 1 */
55#define	CHIP_S_MEM_W1_BUS_START(v)					\
56	    HAE_MEM_REG1_START(((struct cia_config *)(v))->cc_hae_mem)
57#define	CHIP_S_MEM_W1_BUS_END(v)					\
58	    (CHIP_S_MEM_W1_BUS_START(v) + HAE_MEM_REG1_MASK)
59#define	CHIP_S_MEM_W1_SYS_START(v)					\
60	    CIA_PCI_SMEM1
61#define	CHIP_S_MEM_W1_SYS_END(v)					\
62	    (CIA_PCI_SMEM1 + ((HAE_MEM_REG1_MASK + 1) << 5) - 1)
63
64/* Sparse region 2 */
65#define	CHIP_S_MEM_W2_BUS_START(v)					\
66	    HAE_MEM_REG2_START(((struct cia_config *)(v))->cc_hae_mem)
67#define	CHIP_S_MEM_W2_BUS_END(v)					\
68	    (CHIP_S_MEM_W2_BUS_START(v) + HAE_MEM_REG2_MASK)
69#define	CHIP_S_MEM_W2_SYS_START(v)					\
70	    CIA_PCI_SMEM2
71#define	CHIP_S_MEM_W2_SYS_END(v)					\
72	    (CIA_PCI_SMEM2 + ((HAE_MEM_REG2_MASK + 1) << 5) - 1)
73
74/* Sparse region 3 */
75#define	CHIP_S_MEM_W3_BUS_START(v)					\
76	    HAE_MEM_REG3_START(((struct cia_config *)(v))->cc_hae_mem)
77#define	CHIP_S_MEM_W3_BUS_END(v)					\
78	    (CHIP_S_MEM_W3_BUS_START(v) + HAE_MEM_REG3_MASK)
79#define	CHIP_S_MEM_W3_SYS_START(v)					\
80	    CIA_PCI_SMEM3
81#define	CHIP_S_MEM_W3_SYS_END(v)					\
82	    (CIA_PCI_SMEM3 + ((HAE_MEM_REG3_MASK + 1) << 5) - 1)
83
84#include "pcs_bus_mem_common.c"
85