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ciareg.h revision 1.7.2.1 
      1  1.7.2.1  cgd /* $NetBSD: ciareg.h,v 1.7.2.1 1997/06/01 04:13:09 cgd Exp $ */
      2      1.1  cgd 
      3      1.1  cgd /*
      4      1.4  cgd  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
      5      1.1  cgd  * All rights reserved.
      6      1.1  cgd  *
      7      1.1  cgd  * Author: Chris G. Demetriou
      8      1.1  cgd  *
      9      1.1  cgd  * Permission to use, copy, modify and distribute this software and
     10      1.1  cgd  * its documentation is hereby granted, provided that both the copyright
     11      1.1  cgd  * notice and this permission notice appear in all copies of the
     12      1.1  cgd  * software, derivative works or modified versions, and any portions
     13      1.1  cgd  * thereof, and that both notices appear in supporting documentation.
     14      1.1  cgd  *
     15      1.1  cgd  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16      1.1  cgd  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17      1.1  cgd  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18      1.1  cgd  *
     19      1.1  cgd  * Carnegie Mellon requests users of this software to return to
     20      1.1  cgd  *
     21      1.1  cgd  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22      1.1  cgd  *  School of Computer Science
     23      1.1  cgd  *  Carnegie Mellon University
     24      1.1  cgd  *  Pittsburgh PA 15213-3890
     25      1.1  cgd  *
     26      1.1  cgd  * any improvements or extensions that they make and grant Carnegie the
     27      1.1  cgd  * rights to redistribute these changes.
     28      1.1  cgd  */
     29      1.1  cgd 
     30      1.1  cgd /*
     31      1.1  cgd  * 21171 Chipset registers and constants.
     32      1.1  cgd  *
     33      1.1  cgd  * Taken from XXX
     34      1.1  cgd  */
     35      1.1  cgd 
     36      1.5  cgd #define	REGVAL(r)	(*(int32_t *)ALPHA_PHYS_TO_K0SEG(r))
     37      1.1  cgd 
     38      1.1  cgd /*
     39      1.1  cgd  * Base addresses
     40      1.1  cgd  */
     41      1.6  cgd #define	CIA_PCI_SMEM1	0x8000000000UL
     42      1.6  cgd #define	CIA_PCI_SMEM2	0x8400000000UL
     43      1.6  cgd #define	CIA_PCI_SMEM3	0x8500000000UL
     44      1.6  cgd #define	CIA_PCI_SIO1	0x8580000000UL
     45      1.6  cgd #define	CIA_PCI_SIO2	0x85c0000000UL
     46      1.6  cgd #define	CIA_PCI_DENSE	0x8600000000UL
     47      1.6  cgd #define	CIA_PCI_CONF	0x8700000000UL
     48      1.6  cgd #define	CIA_PCI_IACK	0x8720000000UL
     49      1.6  cgd #define	CIA_CSRS	0x8740000000UL
     50      1.6  cgd #define	CIA_PCI_MC_CSRS	0x8750000000UL
     51      1.6  cgd #define	CIA_PCI_ATRANS	0x8760000000UL
     52      1.2  cgd 
     53      1.2  cgd /*
     54      1.2  cgd  * General CSRs
     55      1.2  cgd  */
     56      1.2  cgd 
     57      1.2  cgd #define	CIA_CSR_HAE_MEM	(CIA_CSRS + 0x400)
     58      1.2  cgd 
     59      1.6  cgd #define		HAE_MEM_REG1_START(x)	(((u_int32_t)(x) & 0xe0000000UL) << 0)
     60      1.6  cgd #define		HAE_MEM_REG1_MASK	0x1fffffffUL
     61      1.6  cgd #define		HAE_MEM_REG2_START(x)	(((u_int32_t)(x) & 0x0000f800UL) << 16)
     62      1.6  cgd #define		HAE_MEM_REG2_MASK	0x07ffffffUL
     63      1.7  cgd #define		HAE_MEM_REG3_START(x)	(((u_int32_t)(x) & 0x000000fcUL) << 24)
     64      1.6  cgd #define		HAE_MEM_REG3_MASK	0x03ffffffUL
     65      1.2  cgd 
     66      1.2  cgd #define	CIA_CSR_HAE_IO	(CIA_CSRS + 0x440)
     67      1.3  cgd 
     68      1.6  cgd #define		HAE_IO_REG1_START(x)	0UL
     69      1.6  cgd #define		HAE_IO_REG1_MASK	0x01ffffffUL
     70      1.6  cgd #define		HAE_IO_REG2_START(x)	(((u_int32_t)(x) & 0xfe000000UL) << 0)
     71      1.6  cgd #define		HAE_IO_REG2_MASK	0x01ffffffUL
     72      1.7  cgd 
     73      1.7  cgd #define	CIA_CSR_CIA_ERR	(CIA_CSRS + 0x8200)
     74