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ciareg.h revision 1.10 
      1 /* $NetBSD: ciareg.h,v 1.10 1997/06/06 23:54:26 thorpej Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Authors: Chris G. Demetriou, Jason R. Thorpe
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 /*
     31  * 21171 Chipset registers and constants.
     32  *
     33  * Taken from EC-QE18B-TE.
     34  */
     35 
     36 #define	REGVAL(r)	(*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
     37 
     38 /*
     39  * Base addresses
     40  */
     41 #define	CIA_PCI_SMEM1	0x8000000000UL
     42 #define	CIA_PCI_SMEM2	0x8400000000UL
     43 #define	CIA_PCI_SMEM3	0x8500000000UL
     44 #define	CIA_PCI_SIO1	0x8580000000UL
     45 #define	CIA_PCI_SIO2	0x85c0000000UL
     46 #define	CIA_PCI_DENSE	0x8600000000UL
     47 #define	CIA_PCI_CONF	0x8700000000UL
     48 #define	CIA_PCI_IACK	0x8720000000UL
     49 #define	CIA_CSRS	0x8740000000UL
     50 #define	CIA_PCI_MC_CSRS	0x8750000000UL
     51 #define	CIA_PCI_ATRANS	0x8760000000UL
     52 #define	CIA_PCI_TBIA	0x8760000100UL
     53 
     54 #define	CIA_PCI_W0BASE	0x8760000400UL
     55 #define	CIA_PCI_W0MASK	0x8760000440UL
     56 #define	CIA_PCI_T0BASE	0x8760000480UL
     57 
     58 #define	CIA_PCI_W1BASE	0x8760000500UL
     59 #define	CIA_PCI_W1MASK	0x8760000540UL
     60 #define	CIA_PCI_T1BASE	0x8760000580UL
     61 
     62 #define	CIA_PCI_W2BASE	0x8760000600UL
     63 #define	CIA_PCI_W2MASK	0x8760000640UL
     64 #define	CIA_PCI_T2BASE	0x8760000680UL
     65 
     66 #define	CIA_PCI_W3BASE	0x8760000700UL
     67 #define	CIA_PCI_W3MASK	0x8760000740UL
     68 #define	CIA_PCI_T3BASE	0x8760000780UL
     69 
     70 /*
     71  * Values for CIA_PCI_TBIA
     72  */
     73 #define	CIA_PCI_TBIA_NOOP	0	/* no operation */
     74 #define	CIA_PCI_TBIA_LOCKED	1	/* invalidate and unlock locked tags */
     75 #define	CIA_PCI_TBIA_UNLOCKED	2	/* invalidate unlocked tags */
     76 #define	CIA_PCI_TBIA_ALL	3	/* invalidate and unlock all tags */
     77 
     78 /*
     79  * Values for CIA_PCI_WnBASE
     80  */
     81 #define	CIA_PCI_WnBASE_W_BASE	0xfff00000
     82 #define	CIA_PCI_WnBASE_DAC_EN	0x00000008	/* W3BASE only */
     83 #define	CIA_PCI_WnBASE_MEMCS_EN	0x00000004	/* W0BASE only */
     84 #define	CIA_PCI_WnBASE_SG_EN	0x00000002
     85 #define	CIA_PCI_WnBASE_W_EN	0x00000001
     86 
     87 /*
     88  * Values for CIA_PCI_WnMASK
     89  */
     90 #define	CIA_PCI_WnMASK_W_MASK	0xfff00000
     91 #define	CIA_PCI_WnMASK_1M	0x00000000
     92 #define	CIA_PCI_WnMASK_2M	0x00100000
     93 #define	CIA_PCI_WnMASK_4M	0x00300000
     94 #define	CIA_PCI_WnMASK_8M	0x00700000
     95 #define	CIA_PCI_WnMASK_16M	0x00f00000
     96 #define	CIA_PCI_WnMASK_32M	0x01f00000
     97 #define	CIA_PCI_WnMASK_64M	0x03f00000
     98 #define	CIA_PCI_WnMASK_128M	0x07f00000
     99 #define	CIA_PCI_WnMASK_256M	0x0ff00000
    100 #define	CIA_PCI_WnMASK_512M	0x1ff00000
    101 #define	CIA_PCI_WnMASK_1G	0x3ff00000
    102 #define	CIA_PCI_WnMASK_2G	0x7ff00000
    103 #define	CIA_PCI_WnMASK_4G	0xfff00000
    104 
    105 /*
    106  * Values for CIA_PCI_TnBASE
    107  */
    108 #define	CIA_PCI_TnBASE_MASK	0xfffffff0
    109 #define	CIA_PCI_TnBASE_SHIFT	2
    110 
    111 /*
    112  * General CSRs
    113  */
    114 
    115 #define	CIA_CSR_HAE_MEM	(CIA_CSRS + 0x400)
    116 
    117 #define		HAE_MEM_REG1_START(x)	(((u_int32_t)(x) & 0xe0000000UL) << 0)
    118 #define		HAE_MEM_REG1_MASK	0x1fffffffUL
    119 #define		HAE_MEM_REG2_START(x)	(((u_int32_t)(x) & 0x0000f800UL) << 16)
    120 #define		HAE_MEM_REG2_MASK	0x07ffffffUL
    121 #define		HAE_MEM_REG3_START(x)	(((u_int32_t)(x) & 0x000000fcUL) << 24)
    122 #define		HAE_MEM_REG3_MASK	0x03ffffffUL
    123 
    124 #define	CIA_CSR_HAE_IO	(CIA_CSRS + 0x440)
    125 
    126 #define		HAE_IO_REG1_START(x)	0UL
    127 #define		HAE_IO_REG1_MASK	0x01ffffffUL
    128 #define		HAE_IO_REG2_START(x)	(((u_int32_t)(x) & 0xfe000000UL) << 0)
    129 #define		HAE_IO_REG2_MASK	0x01ffffffUL
    130 
    131 #define	CIA_CSR_CIA_ERR	(CIA_CSRS + 0x8200)
    132