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dwlpx.c revision 1.24 
      1 /* $NetBSD: dwlpx.c,v 1.24 2002/05/16 01:01:31 thorpej Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1997 by Matthew Jacob
      5  * NASA AMES Research Center.
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice immediately at the beginning of the file, without modification,
     13  *    this list of conditions, and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
     24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     30  * SUCH DAMAGE.
     31  */
     32 
     33 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     34 
     35 __KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.24 2002/05/16 01:01:31 thorpej Exp $");
     36 
     37 #include <sys/param.h>
     38 #include <sys/systm.h>
     39 #include <sys/kernel.h>
     40 #include <sys/device.h>
     41 
     42 #include <uvm/uvm_extern.h>
     43 
     44 #include <machine/autoconf.h>
     45 
     46 #include <dev/pci/pcireg.h>
     47 #include <dev/pci/pcivar.h>
     48 
     49 #include <alpha/tlsb/tlsbreg.h>
     50 #include <alpha/tlsb/kftxxvar.h>
     51 #include <alpha/tlsb/kftxxreg.h>
     52 #include <alpha/pci/dwlpxreg.h>
     53 #include <alpha/pci/dwlpxvar.h>
     54 #include <alpha/pci/pci_kn8ae.h>
     55 
     56 #define	KV(_addr)	((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr)))
     57 #define	DWLPX_SYSBASE(sc)	\
     58 	    ((((unsigned long)((sc)->dwlpx_node - 4))	<< 36) |	\
     59 	     (((unsigned long) (sc)->dwlpx_hosenum)	<< 34) |	\
     60 	     (1LL					<< 39))
     61 
     62 
     63 static int	dwlpxmatch __P((struct device *, struct cfdata *, void *));
     64 static void	dwlpxattach __P((struct device *, struct device *, void *));
     65 struct cfattach dwlpx_ca = {
     66 	sizeof(struct dwlpx_softc), dwlpxmatch, dwlpxattach
     67 };
     68 
     69 extern struct cfdriver dwlpx_cd;
     70 
     71 static int	dwlpxprint __P((void *, const char *));
     72 
     73 void	dwlpx_errintr(void *, u_long vec);
     74 
     75 static int
     76 dwlpxprint(aux, pnp)
     77 	void *aux;
     78 	const char *pnp;
     79 {
     80 	register struct pcibus_attach_args *pba = aux;
     81 	/* only PCIs can attach to DWLPX's; easy. */
     82 	if (pnp)
     83 		printf("%s at %s", pba->pba_busname, pnp);
     84 	printf(" bus %d", pba->pba_bus);
     85 	return (UNCONF);
     86 }
     87 
     88 static int
     89 dwlpxmatch(parent, cf, aux)
     90 	struct device *parent;
     91 	struct cfdata *cf;
     92 	void *aux;
     93 {
     94 	struct kft_dev_attach_args *ka = aux;
     95 
     96 	if (strcmp(ka->ka_name, dwlpx_cd.cd_name) != 0)
     97 		return (0);
     98 	return (1);
     99 }
    100 
    101 static void
    102 dwlpxattach(parent, self, aux)
    103 	struct device *parent;
    104 	struct device *self;
    105 	void *aux;
    106 {
    107 	static int once = 0;
    108 	struct dwlpx_softc *sc = (struct dwlpx_softc *)self;
    109 	struct dwlpx_config *ccp = &sc->dwlpx_cc;
    110 	struct kft_dev_attach_args *ka = aux;
    111 	struct pcibus_attach_args pba;
    112 	u_int32_t pcia_present;
    113 
    114 	sc->dwlpx_node = ka->ka_node;
    115 	sc->dwlpx_dtype = ka->ka_dtype;
    116 	sc->dwlpx_hosenum = ka->ka_hosenum;
    117 
    118 	dwlpx_init(sc);
    119 	dwlpx_dma_init(ccp);
    120 
    121 	pcia_present = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
    122 	printf(": PCIA rev. %d, STD I/O %spresent, %dK S/G entries\n",
    123 	    (pcia_present >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK,
    124 	    (pcia_present & PCIA_PRESENT_STDIO) == 0 ? "not " : "",
    125 	    sc->dwlpx_sgmapsz == DWLPX_SG128K ? 128 : 32);
    126 
    127 #if 0
    128 	{
    129 		int hpc, slot, slotval;
    130 		const char *str;
    131 		for (hpc = 0; hpc < sc->dwlpx_nhpc; hpc++) {
    132 			for (slot = 0; slot < 4; slot++) {
    133 				slotval = (pcia_present >>
    134 				    PCIA_PRESENT_SLOTSHIFT(hpc, slot)) &
    135 				    PCIA_PRESENT_SLOT_MASK;
    136 				if (slotval == PCIA_PRESENT_SLOT_NONE)
    137 					continue;
    138 				switch (slotval) {
    139 				case PCIA_PRESENT_SLOT_25W:
    140 					str = "25";
    141 					break;
    142 				case PCIA_PRESENT_SLOT_15W:
    143 					str = "15";
    144 					break;
    145 				case PCIA_PRESENT_SLOW_7W:
    146 				default:		/* XXX gcc */
    147 					str = "7.5";
    148 					break;
    149 				}
    150 				printf("%s: hpc %d slot %d: %s watt module\n",
    151 				    sc->dwlpx_dev.dv_xname, hpc, slot, str);
    152 			}
    153 		}
    154 	}
    155 #endif
    156 
    157 	if (once == 0) {
    158 		/*
    159 		 * Set up interrupts
    160 		 */
    161 		pci_kn8ae_pickintr(&sc->dwlpx_cc, 1);
    162 		once++;
    163 	} else {
    164 		pci_kn8ae_pickintr(&sc->dwlpx_cc, 0);
    165 	}
    166 
    167 	/*
    168 	 * Attach PCI bus
    169 	 */
    170 	pba.pba_busname = "pci";
    171 	pba.pba_iot = &sc->dwlpx_cc.cc_iot;
    172 	pba.pba_memt = &sc->dwlpx_cc.cc_memt;
    173 	pba.pba_dmat =	/* start with direct, may change... */
    174 	    alphabus_dma_get_tag(&sc->dwlpx_cc.cc_dmat_direct, ALPHA_BUS_PCI);
    175 	pba.pba_pc = &sc->dwlpx_cc.cc_pc;
    176 	pba.pba_bus = 0;
    177 	pba.pba_bridgetag = NULL;
    178 	pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
    179 	    PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
    180 	config_found(self, &pba, dwlpxprint);
    181 }
    182 
    183 void
    184 dwlpx_init(sc)
    185 	struct dwlpx_softc *sc;
    186 {
    187 	u_int32_t ctl;
    188 	struct dwlpx_config *ccp = &sc->dwlpx_cc;
    189 	unsigned long vec, ls = DWLPX_SYSBASE(sc);
    190 	int i;
    191 
    192 	if (ccp->cc_initted == 0) {
    193 		/*
    194 		 * On reads, you get a fault if you read a nonexisted HPC.
    195 		 * We know the internal KFTIA hose (hose 0) has only 2 HPCs,
    196 		 * but we can also actually probe for HPCs.
    197 		 * Assume at least one.
    198 		 */
    199 		for (sc->dwlpx_nhpc = 1; sc->dwlpx_nhpc < NHPC;
    200 		    sc->dwlpx_nhpc++) {
    201 			if (badaddr(KV(PCIA_CTL(sc->dwlpx_nhpc) + ls),
    202 			    sizeof (ctl)) != 0) {
    203 				break;
    204 			}
    205 		}
    206 		if (sc->dwlpx_nhpc != NHPC) {
    207 			/* clear (potential) Illegal CSR Address Error */
    208 			REGVAL(PCIA_ERR(0) + DWLPX_SYSBASE(sc)) =
    209 				PCIA_ERR_ALLERR;
    210 		}
    211 
    212 		dwlpx_bus_io_init(&ccp->cc_iot, ccp);
    213 		dwlpx_bus_mem_init(&ccp->cc_memt, ccp);
    214 	}
    215 	dwlpx_pci_init(&ccp->cc_pc, ccp);
    216 	ccp->cc_sc = sc;
    217 
    218 	/*
    219 	 * Establish a precalculated base for convenience's sake.
    220 	 */
    221 	ccp->cc_sysbase = ls;
    222 
    223 	/*
    224 	 * If there are only 2 HPCs, then the 'present' register is not
    225 	 * implemented, so there will only ever be 32K SG entries. Otherwise
    226 	 * any revision greater than zero will have 128K entries.
    227 	 */
    228 	ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
    229 	if (sc->dwlpx_nhpc == 2) {
    230 		sc->dwlpx_sgmapsz = DWLPX_SG32K;
    231 #if 0
    232 	/*
    233 	 * As of 2/25/98- When I enable SG128K, and then have to flip
    234 	 * TBIT below, I get bad SGRAM errors. We'll fix this later
    235 	 * if this gets important.
    236 	 */
    237 	} else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
    238 		sc->dwlpx_sgmapsz = DWLPX_SG128K;
    239 #endif
    240 	} else {
    241 		sc->dwlpx_sgmapsz = DWLPX_SG32K;
    242 	}
    243 
    244 	/*
    245 	 * Set up interrupt stuff for this DWLPX.
    246 	 *
    247 	 * Note that all PCI interrupt pins are disabled at this time.
    248 	 *
    249 	 * Do this even for all HPCs- even for the nonexistent
    250 	 * one on hose zero of a KFTIA.
    251 	 */
    252 	vec = scb_alloc(dwlpx_errintr, sc);
    253 	if (vec == SCB_ALLOC_FAILED)
    254 		panic("%s: unable to allocate error vector",
    255 		    sc->dwlpx_dev.dv_xname);
    256 	printf("%s: error interrupt at vector 0x%lx\n",
    257 	    sc->dwlpx_dev.dv_xname, vec);
    258 	for (i = 0; i < NHPC; i++) {
    259 		REGVAL(PCIA_IMASK(i) + ccp->cc_sysbase) = DWLPX_IMASK_DFLT;
    260 		REGVAL(PCIA_ERRVEC(i) + ccp->cc_sysbase) = vec;
    261 	}
    262 
    263 	/*
    264 	 * Establish HAE values, as well as make sure of sanity elsewhere.
    265 	 */
    266 	for (i = 0; i < sc->dwlpx_nhpc; i++) {
    267 		ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
    268 		ctl &= 0x0fffffff;
    269 		ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
    270 		/*
    271 		 * I originally also had it or'ing in 3, which makes no sense.
    272 		 */
    273 
    274 		ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB;
    275 
    276 		/*
    277 		 * Only valid if we're attached to a KFTIA or a KTHA.
    278 		 */
    279 		ctl |= PCIA_CTL_3UP;
    280 
    281 		ctl |= PCIA_CTL_CUTENA;
    282 
    283 		/*
    284 		 * Fit in appropriate S/G Map Ram size.
    285 		 */
    286 		if (sc->dwlpx_sgmapsz == DWLPX_SG32K)
    287 			ctl |= PCIA_CTL_SG32K;
    288 		else if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
    289 			ctl |= PCIA_CTL_SG128K;
    290 		else
    291 			ctl |= PCIA_CTL_SG32K;
    292 
    293 		REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl;
    294 	}
    295 	/*
    296 	 * Enable TBIT if required
    297 	 */
    298 	if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
    299 		REGVAL(PCIA_TBIT + ccp->cc_sysbase) = 1;
    300 	alpha_mb();
    301 	ccp->cc_initted = 1;
    302 }
    303 
    304 void
    305 dwlpx_errintr(arg, vec)
    306 	void *arg;
    307 	unsigned long vec;
    308 {
    309 	struct dwlpx_softc *sc = arg;
    310 	struct dwlpx_config *ccp = &sc->dwlpx_cc;
    311 	int i;
    312 	struct {
    313 		u_int32_t err;
    314 		u_int32_t addr;
    315 	} hpcs[NHPC];
    316 
    317 	for (i = 0; i < sc->dwlpx_nhpc; i++) {
    318 		hpcs[i].err = REGVAL(PCIA_ERR(i) + ccp->cc_sysbase);
    319 		hpcs[i].addr = REGVAL(PCIA_FADR(i) + ccp->cc_sysbase);
    320 	}
    321 	printf("%s: node %d hose %d error interrupt\n",
    322 	    sc->dwlpx_dev.dv_xname, sc->dwlpx_node, sc->dwlpx_hosenum);
    323 
    324 	for (i = 0; i < sc->dwlpx_nhpc; i++) {
    325 		if ((hpcs[i].err & PCIA_ERR_ERROR) == 0)
    326 			continue;
    327 		printf("\tHPC %d: ERR=0x%08x; DMA %s Memory, "
    328 			"Failing Address 0x%x\n",
    329 			i, hpcs[i].err, hpcs[i].addr & 0x1? "write to" :
    330 			"read from", hpcs[i].addr & ~3);
    331 		if (hpcs[i].err & PCIA_ERR_SERR_L)
    332 			printf("\t       PCI device asserted SERR_L\n");
    333 		if (hpcs[i].err & PCIA_ERR_ILAT)
    334 			printf("\t       Incremental Latency Exceeded\n");
    335 		if (hpcs[i].err & PCIA_ERR_SGPRTY)
    336 			printf("\t       CPU access of SG RAM Parity Error\n");
    337 		if (hpcs[i].err & PCIA_ERR_ILLCSR)
    338 			printf("\t       Illegal CSR Address Error\n");
    339 		if (hpcs[i].err & PCIA_ERR_PCINXM)
    340 			printf("\t       Nonexistent PCI Address Error\n");
    341 		if (hpcs[i].err & PCIA_ERR_DSCERR)
    342 			printf("\t       PCI Target Disconnect Error\n");
    343 		if (hpcs[i].err & PCIA_ERR_ABRT)
    344 			printf("\t       PCI Target Abort Error\n");
    345 		if (hpcs[i].err & PCIA_ERR_WPRTY)
    346 			printf("\t       PCI Write Parity Error\n");
    347 		if (hpcs[i].err & PCIA_ERR_DPERR)
    348 			printf("\t       PCI Data Parity Error\n");
    349 		if (hpcs[i].err & PCIA_ERR_APERR)
    350 			printf("\t       PCI Address Parity Error\n");
    351 		if (hpcs[i].err & PCIA_ERR_DFLT)
    352 			printf("\t       SG Map RAM Invalid Entry Error\n");
    353 		if (hpcs[i].err & PCIA_ERR_DPRTY)
    354 			printf("\t       DMA access of SG RAM Parity Error\n");
    355 		if (hpcs[i].err & PCIA_ERR_DRPERR)
    356 			printf("\t       DMA Read Return Parity Error\n");
    357 		if (hpcs[i].err & PCIA_ERR_MABRT)
    358 			printf("\t       PCI Master Abort Error\n");
    359 		if (hpcs[i].err & PCIA_ERR_CPRTY)
    360 			printf("\t       CSR Parity Error\n");
    361 		if (hpcs[i].err & PCIA_ERR_COVR)
    362 			printf("\t       CSR Overrun Error\n");
    363 		if (hpcs[i].err & PCIA_ERR_MBPERR)
    364 			printf("\t       Mailbox Parity Error\n");
    365 		if (hpcs[i].err & PCIA_ERR_MBILI)
    366 			printf("\t       Mailbox Illegal Length Error\n");
    367 		REGVAL(PCIA_ERR(i) + ccp->cc_sysbase) = hpcs[i].err;
    368 	}
    369 }
    370