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dwlpx.c revision 1.29 
      1 /* $NetBSD: dwlpx.c,v 1.29 2004/08/30 15:05:16 drochner Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1997 by Matthew Jacob
      5  * NASA AMES Research Center.
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice immediately at the beginning of the file, without modification,
     13  *    this list of conditions, and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
     24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     30  * SUCH DAMAGE.
     31  */
     32 
     33 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     34 
     35 __KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.29 2004/08/30 15:05:16 drochner Exp $");
     36 
     37 #include <sys/param.h>
     38 #include <sys/systm.h>
     39 #include <sys/kernel.h>
     40 #include <sys/device.h>
     41 
     42 #include <uvm/uvm_extern.h>
     43 
     44 #include <machine/autoconf.h>
     45 
     46 #include <dev/pci/pcireg.h>
     47 #include <dev/pci/pcivar.h>
     48 
     49 #include <alpha/tlsb/tlsbreg.h>
     50 #include <alpha/tlsb/kftxxvar.h>
     51 #include <alpha/tlsb/kftxxreg.h>
     52 #include <alpha/pci/dwlpxreg.h>
     53 #include <alpha/pci/dwlpxvar.h>
     54 #include <alpha/pci/pci_kn8ae.h>
     55 
     56 #define	KV(_addr)	((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr)))
     57 #define	DWLPX_SYSBASE(sc)	\
     58 	    ((((unsigned long)((sc)->dwlpx_node - 4))	<< 36) |	\
     59 	     (((unsigned long) (sc)->dwlpx_hosenum)	<< 34) |	\
     60 	     (1LL					<< 39))
     61 
     62 
     63 static int	dwlpxmatch __P((struct device *, struct cfdata *, void *));
     64 static void	dwlpxattach __P((struct device *, struct device *, void *));
     65 CFATTACH_DECL(dwlpx, sizeof(struct dwlpx_softc),
     66     dwlpxmatch, dwlpxattach, NULL, NULL);
     67 
     68 extern struct cfdriver dwlpx_cd;
     69 
     70 void	dwlpx_errintr(void *, u_long vec);
     71 
     72 static int
     73 dwlpxmatch(parent, cf, aux)
     74 	struct device *parent;
     75 	struct cfdata *cf;
     76 	void *aux;
     77 {
     78 	struct kft_dev_attach_args *ka = aux;
     79 
     80 	if (strcmp(ka->ka_name, dwlpx_cd.cd_name) != 0)
     81 		return (0);
     82 	return (1);
     83 }
     84 
     85 static void
     86 dwlpxattach(parent, self, aux)
     87 	struct device *parent;
     88 	struct device *self;
     89 	void *aux;
     90 {
     91 	static int once = 0;
     92 	struct dwlpx_softc *sc = (struct dwlpx_softc *)self;
     93 	struct dwlpx_config *ccp = &sc->dwlpx_cc;
     94 	struct kft_dev_attach_args *ka = aux;
     95 	struct pcibus_attach_args pba;
     96 	u_int32_t pcia_present;
     97 
     98 	sc->dwlpx_node = ka->ka_node;
     99 	sc->dwlpx_dtype = ka->ka_dtype;
    100 	sc->dwlpx_hosenum = ka->ka_hosenum;
    101 
    102 	dwlpx_init(sc);
    103 	dwlpx_dma_init(ccp);
    104 
    105 	pcia_present = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
    106 	printf(": PCIA rev. %d, STD I/O %spresent, %dK S/G entries\n",
    107 	    (pcia_present >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK,
    108 	    (pcia_present & PCIA_PRESENT_STDIO) == 0 ? "not " : "",
    109 	    sc->dwlpx_sgmapsz == DWLPX_SG128K ? 128 : 32);
    110 
    111 #if 0
    112 	{
    113 		int hpc, slot, slotval;
    114 		const char *str;
    115 		for (hpc = 0; hpc < sc->dwlpx_nhpc; hpc++) {
    116 			for (slot = 0; slot < 4; slot++) {
    117 				slotval = (pcia_present >>
    118 				    PCIA_PRESENT_SLOTSHIFT(hpc, slot)) &
    119 				    PCIA_PRESENT_SLOT_MASK;
    120 				if (slotval == PCIA_PRESENT_SLOT_NONE)
    121 					continue;
    122 				switch (slotval) {
    123 				case PCIA_PRESENT_SLOT_25W:
    124 					str = "25";
    125 					break;
    126 				case PCIA_PRESENT_SLOT_15W:
    127 					str = "15";
    128 					break;
    129 				case PCIA_PRESENT_SLOW_7W:
    130 				default:		/* XXX gcc */
    131 					str = "7.5";
    132 					break;
    133 				}
    134 				printf("%s: hpc %d slot %d: %s watt module\n",
    135 				    sc->dwlpx_dev.dv_xname, hpc, slot, str);
    136 			}
    137 		}
    138 	}
    139 #endif
    140 
    141 	if (once == 0) {
    142 		/*
    143 		 * Set up interrupts
    144 		 */
    145 		pci_kn8ae_pickintr(&sc->dwlpx_cc, 1);
    146 		once++;
    147 	} else {
    148 		pci_kn8ae_pickintr(&sc->dwlpx_cc, 0);
    149 	}
    150 
    151 	/*
    152 	 * Attach PCI bus
    153 	 */
    154 	pba.pba_iot = &sc->dwlpx_cc.cc_iot;
    155 	pba.pba_memt = &sc->dwlpx_cc.cc_memt;
    156 	pba.pba_dmat =	/* start with direct, may change... */
    157 	    alphabus_dma_get_tag(&sc->dwlpx_cc.cc_dmat_direct, ALPHA_BUS_PCI);
    158 	pba.pba_dmat64 = NULL;
    159 	pba.pba_pc = &sc->dwlpx_cc.cc_pc;
    160 	pba.pba_bus = 0;
    161 	pba.pba_bridgetag = NULL;
    162 	pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
    163 	    PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
    164 	config_found_ia(self, "pcibus", &pba, pcibusprint);
    165 }
    166 
    167 void
    168 dwlpx_init(sc)
    169 	struct dwlpx_softc *sc;
    170 {
    171 	u_int32_t ctl;
    172 	struct dwlpx_config *ccp = &sc->dwlpx_cc;
    173 	unsigned long vec, ls = DWLPX_SYSBASE(sc);
    174 	int i;
    175 
    176 	if (ccp->cc_initted == 0) {
    177 		/*
    178 		 * On reads, you get a fault if you read a nonexisted HPC.
    179 		 * We know the internal KFTIA hose (hose 0) has only 2 HPCs,
    180 		 * but we can also actually probe for HPCs.
    181 		 * Assume at least one.
    182 		 */
    183 		for (sc->dwlpx_nhpc = 1; sc->dwlpx_nhpc < NHPC;
    184 		    sc->dwlpx_nhpc++) {
    185 			if (badaddr(KV(PCIA_CTL(sc->dwlpx_nhpc) + ls),
    186 			    sizeof (ctl)) != 0) {
    187 				break;
    188 			}
    189 		}
    190 		if (sc->dwlpx_nhpc != NHPC) {
    191 			/* clear (potential) Illegal CSR Address Error */
    192 			REGVAL(PCIA_ERR(0) + DWLPX_SYSBASE(sc)) =
    193 				PCIA_ERR_ALLERR;
    194 		}
    195 
    196 		dwlpx_bus_io_init(&ccp->cc_iot, ccp);
    197 		dwlpx_bus_mem_init(&ccp->cc_memt, ccp);
    198 	}
    199 	dwlpx_pci_init(&ccp->cc_pc, ccp);
    200 	ccp->cc_sc = sc;
    201 
    202 	/*
    203 	 * Establish a precalculated base for convenience's sake.
    204 	 */
    205 	ccp->cc_sysbase = ls;
    206 
    207 	/*
    208 	 * If there are only 2 HPCs, then the 'present' register is not
    209 	 * implemented, so there will only ever be 32K SG entries. Otherwise
    210 	 * any revision greater than zero will have 128K entries.
    211 	 */
    212 	ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
    213 	if (sc->dwlpx_nhpc == 2) {
    214 		sc->dwlpx_sgmapsz = DWLPX_SG32K;
    215 #if 0
    216 	/*
    217 	 * As of 2/25/98- When I enable SG128K, and then have to flip
    218 	 * TBIT below, I get bad SGRAM errors. We'll fix this later
    219 	 * if this gets important.
    220 	 */
    221 	} else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
    222 		sc->dwlpx_sgmapsz = DWLPX_SG128K;
    223 #endif
    224 	} else {
    225 		sc->dwlpx_sgmapsz = DWLPX_SG32K;
    226 	}
    227 
    228 	/*
    229 	 * Set up interrupt stuff for this DWLPX.
    230 	 *
    231 	 * Note that all PCI interrupt pins are disabled at this time.
    232 	 *
    233 	 * Do this even for all HPCs- even for the nonexistent
    234 	 * one on hose zero of a KFTIA.
    235 	 */
    236 	vec = scb_alloc(dwlpx_errintr, sc);
    237 	if (vec == SCB_ALLOC_FAILED)
    238 		panic("%s: unable to allocate error vector",
    239 		    sc->dwlpx_dev.dv_xname);
    240 	printf("%s: error interrupt at vector 0x%lx\n",
    241 	    sc->dwlpx_dev.dv_xname, vec);
    242 	for (i = 0; i < NHPC; i++) {
    243 		REGVAL(PCIA_IMASK(i) + ccp->cc_sysbase) = DWLPX_IMASK_DFLT;
    244 		REGVAL(PCIA_ERRVEC(i) + ccp->cc_sysbase) = vec;
    245 	}
    246 
    247 	/*
    248 	 * Establish HAE values, as well as make sure of sanity elsewhere.
    249 	 */
    250 	for (i = 0; i < sc->dwlpx_nhpc; i++) {
    251 		ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
    252 		ctl &= 0x0fffffff;
    253 		ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
    254 		/*
    255 		 * I originally also had it or'ing in 3, which makes no sense.
    256 		 */
    257 
    258 		ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB;
    259 
    260 		/*
    261 		 * Only valid if we're attached to a KFTIA or a KTHA.
    262 		 */
    263 		ctl |= PCIA_CTL_3UP;
    264 
    265 		ctl |= PCIA_CTL_CUTENA;
    266 
    267 		/*
    268 		 * Fit in appropriate S/G Map Ram size.
    269 		 */
    270 		if (sc->dwlpx_sgmapsz == DWLPX_SG32K)
    271 			ctl |= PCIA_CTL_SG32K;
    272 		else if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
    273 			ctl |= PCIA_CTL_SG128K;
    274 		else
    275 			ctl |= PCIA_CTL_SG32K;
    276 
    277 		REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl;
    278 	}
    279 	/*
    280 	 * Enable TBIT if required
    281 	 */
    282 	if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
    283 		REGVAL(PCIA_TBIT + ccp->cc_sysbase) = 1;
    284 	alpha_mb();
    285 	ccp->cc_initted = 1;
    286 }
    287 
    288 void
    289 dwlpx_errintr(arg, vec)
    290 	void *arg;
    291 	unsigned long vec;
    292 {
    293 	struct dwlpx_softc *sc = arg;
    294 	struct dwlpx_config *ccp = &sc->dwlpx_cc;
    295 	int i;
    296 	struct {
    297 		u_int32_t err;
    298 		u_int32_t addr;
    299 	} hpcs[NHPC];
    300 
    301 	for (i = 0; i < sc->dwlpx_nhpc; i++) {
    302 		hpcs[i].err = REGVAL(PCIA_ERR(i) + ccp->cc_sysbase);
    303 		hpcs[i].addr = REGVAL(PCIA_FADR(i) + ccp->cc_sysbase);
    304 	}
    305 	printf("%s: node %d hose %d error interrupt\n",
    306 	    sc->dwlpx_dev.dv_xname, sc->dwlpx_node, sc->dwlpx_hosenum);
    307 
    308 	for (i = 0; i < sc->dwlpx_nhpc; i++) {
    309 		if ((hpcs[i].err & PCIA_ERR_ERROR) == 0)
    310 			continue;
    311 		printf("\tHPC %d: ERR=0x%08x; DMA %s Memory, "
    312 			"Failing Address 0x%x\n",
    313 			i, hpcs[i].err, hpcs[i].addr & 0x1? "write to" :
    314 			"read from", hpcs[i].addr & ~3);
    315 		if (hpcs[i].err & PCIA_ERR_SERR_L)
    316 			printf("\t       PCI device asserted SERR_L\n");
    317 		if (hpcs[i].err & PCIA_ERR_ILAT)
    318 			printf("\t       Incremental Latency Exceeded\n");
    319 		if (hpcs[i].err & PCIA_ERR_SGPRTY)
    320 			printf("\t       CPU access of SG RAM Parity Error\n");
    321 		if (hpcs[i].err & PCIA_ERR_ILLCSR)
    322 			printf("\t       Illegal CSR Address Error\n");
    323 		if (hpcs[i].err & PCIA_ERR_PCINXM)
    324 			printf("\t       Nonexistent PCI Address Error\n");
    325 		if (hpcs[i].err & PCIA_ERR_DSCERR)
    326 			printf("\t       PCI Target Disconnect Error\n");
    327 		if (hpcs[i].err & PCIA_ERR_ABRT)
    328 			printf("\t       PCI Target Abort Error\n");
    329 		if (hpcs[i].err & PCIA_ERR_WPRTY)
    330 			printf("\t       PCI Write Parity Error\n");
    331 		if (hpcs[i].err & PCIA_ERR_DPERR)
    332 			printf("\t       PCI Data Parity Error\n");
    333 		if (hpcs[i].err & PCIA_ERR_APERR)
    334 			printf("\t       PCI Address Parity Error\n");
    335 		if (hpcs[i].err & PCIA_ERR_DFLT)
    336 			printf("\t       SG Map RAM Invalid Entry Error\n");
    337 		if (hpcs[i].err & PCIA_ERR_DPRTY)
    338 			printf("\t       DMA access of SG RAM Parity Error\n");
    339 		if (hpcs[i].err & PCIA_ERR_DRPERR)
    340 			printf("\t       DMA Read Return Parity Error\n");
    341 		if (hpcs[i].err & PCIA_ERR_MABRT)
    342 			printf("\t       PCI Master Abort Error\n");
    343 		if (hpcs[i].err & PCIA_ERR_CPRTY)
    344 			printf("\t       CSR Parity Error\n");
    345 		if (hpcs[i].err & PCIA_ERR_COVR)
    346 			printf("\t       CSR Overrun Error\n");
    347 		if (hpcs[i].err & PCIA_ERR_MBPERR)
    348 			printf("\t       Mailbox Parity Error\n");
    349 		if (hpcs[i].err & PCIA_ERR_MBILI)
    350 			printf("\t       Mailbox Illegal Length Error\n");
    351 		REGVAL(PCIA_ERR(i) + ccp->cc_sysbase) = hpcs[i].err;
    352 	}
    353 }
    354