dwlpx.c revision 1.3
1 /* $NetBSD: dwlpx.c,v 1.3 1997/04/07 02:01:17 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1997 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <machine/options.h> /* Pull in config options headers */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <vm/vm.h> 40 41 #include <machine/autoconf.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <alpha/tlsb/tlsbreg.h> 45 #include <alpha/tlsb/kftxxvar.h> 46 #include <alpha/tlsb/kftxxreg.h> 47 #include <alpha/pci/dwlpxreg.h> 48 #include <alpha/pci/dwlpxvar.h> 49 #include <alpha/pci/pci_kn8ae.h> 50 51 #include <alpha/include/pmap.old.h> 52 53 #define KV(_addr) ((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr))) 54 55 static int dwlpxmatch __P((struct device *, struct cfdata *, void *)); 56 static void dwlpxattach __P((struct device *, struct device *, void *)); 57 struct cfattach dwlpx_ca = { 58 sizeof(struct dwlpx_softc), dwlpxmatch, dwlpxattach 59 }; 60 61 struct cfdriver dwlpx_cd = { 62 NULL, "dwlpx", DV_DULL, 63 }; 64 65 static int dwlpxprint __P((void *, const char *)); 66 67 static int 68 dwlpxprint(aux, pnp) 69 void *aux; 70 const char *pnp; 71 { 72 register struct pcibus_attach_args *pba = aux; 73 /* only PCIs can attach to DWLPX's; easy. */ 74 if (pnp) 75 printf("%s at %s", pba->pba_busname, pnp); 76 printf(" bus %d", pba->pba_bus); 77 return (UNCONF); 78 } 79 80 static int 81 dwlpxmatch(parent, cf, aux) 82 struct device *parent; 83 struct cfdata *cf; 84 void *aux; 85 { 86 struct kft_dev_attach_args *ka = aux; 87 88 if (strcmp(ka->ka_name, dwlpx_cd.cd_name) != 0) 89 return (0); 90 return (1); 91 } 92 93 static void 94 dwlpxattach(parent, self, aux) 95 struct device *parent; 96 struct device *self; 97 void *aux; 98 { 99 static int once = 0; 100 struct dwlpx_softc *sc = (struct dwlpx_softc *)self; 101 struct kft_dev_attach_args *ka = aux; 102 struct pcibus_attach_args pba; 103 104 sc->dwlpx_node = ka->ka_node; 105 sc->dwlpx_dtype = ka->ka_dtype; 106 sc->dwlpx_hosenum = ka->ka_hosenum; 107 /* 108 * On reads, you get a fault if you read a nonexisted HPC. 109 * The internal KFTIA hose (hose 0) has only 2 HPCs. 110 */ 111 sc->dwlpx_nhpc = NHPC; 112 if (sc->dwlpx_hosenum == 0) { 113 if (TLDEV_DTYPE(sc->dwlpx_dtype) == TLDEV_DTYPE_KFTIA) { 114 sc->dwlpx_nhpc = NHPC - 1; 115 } 116 } 117 118 dwlpx_init(sc); 119 printf(", hose %d\n", sc->dwlpx_hosenum); 120 if (once == 0) { 121 /* 122 * Set up interrupts 123 */ 124 pci_kn8ae_pickintr(&sc->dwlpx_cc, 1); 125 #ifdef EVCNT_COUNTERS 126 evcnt_attach(self, "intr", kn8ae_intr_evcnt); 127 #endif 128 once++; 129 } else { 130 pci_kn8ae_pickintr(&sc->dwlpx_cc, 0); 131 } 132 133 /* 134 * Attach PCI bus 135 */ 136 pba.pba_busname = "pci"; 137 pba.pba_iot = sc->dwlpx_cc.cc_iot; 138 pba.pba_memt = sc->dwlpx_cc.cc_memt; 139 pba.pba_pc = &sc->dwlpx_cc.cc_pc; 140 pba.pba_bus = 0; 141 config_found(self, &pba, dwlpxprint); 142 } 143 144 void 145 dwlpx_init(sc) 146 struct dwlpx_softc *sc; 147 { 148 int i; 149 struct dwlpx_config *ccp = &sc->dwlpx_cc; 150 151 if (ccp->cc_initted == 0) { 152 ccp->cc_iot = dwlpx_bus_io_init(ccp); 153 ccp->cc_memt = dwlpx_bus_mem_init(ccp); 154 } 155 dwlpx_pci_init(&ccp->cc_pc, ccp); 156 ccp->cc_sc = sc; 157 158 /* 159 * Establish a precalculated base for convenience's sake. 160 */ 161 ccp->cc_sysbase = 162 (((unsigned long)(sc->dwlpx_node - 4)) << 36) | 163 (((unsigned long) sc->dwlpx_hosenum) << 34) | 164 (1LL << 39); 165 166 /* 167 * Set up DMA windows for this DWLPX. 168 * 169 * Basically, we set up for a 1GB direct mapped window, 170 * starting from PCI address 0x40000000. And that's it. 171 * 172 * Do this even for all HPCs- even for the nonexistent 173 * one on hose zero of a KFTIA. 174 */ 175 for (i = 0; i < NHPC; i++) { 176 REGVAL(PCIA_WMASK_A(i) + ccp->cc_sysbase) = 0; 177 REGVAL(PCIA_TBASE_A(i) + ccp->cc_sysbase) = 0; 178 REGVAL(PCIA_WBASE_A(i) + ccp->cc_sysbase) = 0; 179 REGVAL(PCIA_WMASK_B(i) + ccp->cc_sysbase) = 0x3fff0000; 180 REGVAL(PCIA_TBASE_B(i) + ccp->cc_sysbase) = 0; 181 REGVAL(PCIA_WBASE_B(i) + ccp->cc_sysbase) = 0x40000002; 182 REGVAL(PCIA_WMASK_C(i) + ccp->cc_sysbase) = 0; 183 REGVAL(PCIA_TBASE_C(i) + ccp->cc_sysbase) = 0; 184 REGVAL(PCIA_WBASE_C(i) + ccp->cc_sysbase) = 0; 185 } 186 /* XXX XXX BEGIN XXX XXX */ 187 { /* XXX */ 188 extern vm_offset_t alpha_XXX_dmamap_or; /* XXX */ 189 alpha_XXX_dmamap_or = 0x40000000; /* XXX */ 190 } /* XXX */ 191 /* XXX XXX END XXX XXX */ 192 193 /* 194 * Set up interrupt stuff for this DWLPX. 195 * 196 * Note that all PCI interrupt pins are disabled at this time. 197 * 198 * Do this even for all HPCs- even for the nonexistent 199 * one on hose zero of a KFTIA. 200 */ 201 for (i = 0; i < NHPC; i++) { 202 REGVAL(PCIA_IMASK(i) + ccp->cc_sysbase) = DWLPX_IMASK_DFLT; 203 REGVAL(PCIA_ERRVEC(i) + ccp->cc_sysbase) = 204 DWLPX_ERRVEC((sc->dwlpx_node - 4), sc->dwlpx_hosenum); 205 } 206 for (i = 0; i < DWLPX_MAXDEV; i++) { 207 u_int16_t vec; 208 int ss, hpc; 209 210 vec = DWLPX_MVEC((sc->dwlpx_node - 4), sc->dwlpx_hosenum, i); 211 ss = i; 212 if (i < 4) { 213 hpc = 0; 214 } else if (i < 8) { 215 ss -= 4; 216 hpc = 1; 217 } else { 218 ss -= 8; 219 hpc = 2; 220 } 221 REGVAL(PCIA_DEVVEC(hpc, ss, 1) + ccp->cc_sysbase) = vec; 222 REGVAL(PCIA_DEVVEC(hpc, ss, 2) + ccp->cc_sysbase) = vec; 223 REGVAL(PCIA_DEVVEC(hpc, ss, 3) + ccp->cc_sysbase) = vec; 224 REGVAL(PCIA_DEVVEC(hpc, ss, 4) + ccp->cc_sysbase) = vec; 225 } 226 /* 227 * Establish HAE values, as well as make sure of sanity elsewhere. 228 */ 229 for (i = 0; i < sc->dwlpx_nhpc; i++) { 230 u_int32_t ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase); 231 ctl &= 0x0fffffff; 232 ctl &= ~((0x1f << 14) | (0x1f << 9) | 0x3); 233 #if 0 234 ctl |= ((1 << 14) | (1 << 9)); 235 #endif 236 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl; 237 } 238 ccp->cc_initted = 1; 239 } 240
Indexes created Tue Sep 30 17:09:57 GMT 2025