Home | History | Annotate | Line # | Download | only in pci
dwlpx.c revision 1.40 
      1 /* $NetBSD: dwlpx.c,v 1.40 2021/04/24 23:36:23 thorpej Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1997 by Matthew Jacob
      5  * NASA AMES Research Center.
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice immediately at the beginning of the file, without modification,
     13  *    this list of conditions, and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
     24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     30  * SUCH DAMAGE.
     31  */
     32 
     33 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     34 
     35 __KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.40 2021/04/24 23:36:23 thorpej Exp $");
     36 
     37 #include <sys/param.h>
     38 #include <sys/systm.h>
     39 #include <sys/kernel.h>
     40 #include <sys/device.h>
     41 #include <sys/cpu.h>
     42 
     43 #include <machine/autoconf.h>
     44 
     45 #include <dev/pci/pcireg.h>
     46 #include <dev/pci/pcivar.h>
     47 
     48 #include <alpha/tlsb/tlsbreg.h>
     49 #include <alpha/tlsb/kftxxvar.h>
     50 #include <alpha/tlsb/kftxxreg.h>
     51 #include <alpha/pci/dwlpxreg.h>
     52 #include <alpha/pci/dwlpxvar.h>
     53 #include <alpha/pci/pci_kn8ae.h>
     54 
     55 #define	KV(_addr)	((void *)ALPHA_PHYS_TO_K0SEG((_addr)))
     56 #define	DWLPX_SYSBASE(sc)	\
     57 	    ((((unsigned long)((sc)->dwlpx_node - 4))	<< 36) |	\
     58 	     (((unsigned long) (sc)->dwlpx_hosenum)	<< 34) |	\
     59 	     (1LL					<< 39))
     60 #define	DWLPX_SYSBASE1(node, hosenum)	\
     61 	    ((((unsigned long)(node - 4))	<< 36) |	\
     62 	     (((unsigned long) hosenum)	        << 34) |	\
     63 	     (1LL					<< 39))
     64 
     65 
     66 static int	dwlpxmatch(device_t, cfdata_t, void *);
     67 static void	dwlpxattach(device_t, device_t, void *);
     68 
     69 CFATTACH_DECL_NEW(dwlpx, sizeof(struct dwlpx_softc),
     70     dwlpxmatch, dwlpxattach, NULL, NULL);
     71 
     72 extern struct cfdriver dwlpx_cd;
     73 
     74 void	dwlpx_errintr(void *, u_long vec);
     75 
     76 static int
     77 dwlpxmatch(device_t parent, cfdata_t cf, void *aux)
     78 {
     79 	struct kft_dev_attach_args *ka = aux;
     80 	unsigned long ls;
     81 	uint32_t ctl;
     82 
     83 	if (strcmp(ka->ka_name, dwlpx_cd.cd_name) != 0)
     84 		return (0);
     85 
     86 	ls = DWLPX_SYSBASE1(ka->ka_node, ka->ka_hosenum);
     87 
     88 	/*
     89 	 * Probe the first HPC to make sure this really is a dwlpx and
     90 	 * nothing else.
     91 	 */
     92 	if (badaddr(KV(PCIA_CTL(1) + ls), sizeof (ctl)) != 0) {
     93 		/*
     94 		 * If we are here something went wrong. One reason
     95 		 * could be that this is a dwlma and not a dwlpx.
     96 		 *
     97 		 * We can not clear potential illegal CSR errors here
     98 		 * since it is unknown hardware.
     99 		 */
    100 		return (0);
    101 	}
    102 
    103 	return (1);
    104 }
    105 
    106 static void
    107 dwlpxattach(device_t parent, device_t self, void *aux)
    108 {
    109 	static int once = 0;
    110 	struct dwlpx_softc *sc = device_private(self);
    111 	struct dwlpx_config *ccp = &sc->dwlpx_cc;
    112 	struct kft_dev_attach_args *ka = aux;
    113 	struct pcibus_attach_args pba;
    114 	uint32_t pcia_present;
    115 
    116 	sc->dwlpx_dev = self;
    117 	sc->dwlpx_node = ka->ka_node;
    118 	sc->dwlpx_dtype = ka->ka_dtype;
    119 	sc->dwlpx_hosenum = ka->ka_hosenum;
    120 
    121 	dwlpx_init(sc);
    122 	dwlpx_dma_init(ccp);
    123 
    124 	pcia_present = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
    125 	aprint_normal(": PCIA rev. %d, STD I/O %spresent, %dK S/G entries\n",
    126 	    (pcia_present >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK,
    127 	    (pcia_present & PCIA_PRESENT_STDIO) == 0 ? "not " : "",
    128 	    sc->dwlpx_sgmapsz == DWLPX_SG128K ? 128 : 32);
    129 
    130 #if 0
    131 	{
    132 		int hpc, slot, slotval;
    133 		const char *str;
    134 		for (hpc = 0; hpc < sc->dwlpx_nhpc; hpc++) {
    135 			for (slot = 0; slot < 4; slot++) {
    136 				slotval = (pcia_present >>
    137 				    PCIA_PRESENT_SLOTSHIFT(hpc, slot)) &
    138 				    PCIA_PRESENT_SLOT_MASK;
    139 				if (slotval == PCIA_PRESENT_SLOT_NONE)
    140 					continue;
    141 				switch (slotval) {
    142 				case PCIA_PRESENT_SLOT_25W:
    143 					str = "25";
    144 					break;
    145 				case PCIA_PRESENT_SLOT_15W:
    146 					str = "15";
    147 					break;
    148 				case PCIA_PRESENT_SLOW_7W:
    149 				default:		/* XXX gcc */
    150 					str = "7.5";
    151 					break;
    152 				}
    153 				aprint_normal_dev(sc->dwlpx_dev,
    154 				    "hpc %d slot %d: %s watt module\n",
    155 				    hpc, slot, str);
    156 			}
    157 		}
    158 	}
    159 #endif
    160 
    161 	if (once == 0) {
    162 		/*
    163 		 * Set up interrupts
    164 		 */
    165 		pci_kn8ae_pickintr(&sc->dwlpx_cc, 1);
    166 		once++;
    167 	} else {
    168 		pci_kn8ae_pickintr(&sc->dwlpx_cc, 0);
    169 	}
    170 
    171 	/*
    172 	 * Attach PCI bus
    173 	 */
    174 	pba.pba_iot = &sc->dwlpx_cc.cc_iot;
    175 	pba.pba_memt = &sc->dwlpx_cc.cc_memt;
    176 	pba.pba_dmat =	/* start with direct, may change... */
    177 	    alphabus_dma_get_tag(&sc->dwlpx_cc.cc_dmat_direct, ALPHA_BUS_PCI);
    178 	pba.pba_dmat64 = NULL;
    179 	pba.pba_pc = &sc->dwlpx_cc.cc_pc;
    180 	pba.pba_bus = 0;
    181 	pba.pba_bridgetag = NULL;
    182 	pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
    183 	    PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
    184 	config_found(self, &pba, pcibusprint, CFARG_EOL);
    185 }
    186 
    187 void
    188 dwlpx_init(struct dwlpx_softc *sc)
    189 {
    190 	uint32_t ctl;
    191 	struct dwlpx_config *ccp = &sc->dwlpx_cc;
    192 	unsigned long vec, ls = DWLPX_SYSBASE(sc);
    193 	int i;
    194 
    195 	if (ccp->cc_initted == 0) {
    196 		/*
    197 		 * On reads, you get a fault if you read a nonexisted HPC.
    198 		 * We know the internal KFTIA hose (hose 0) has only 2 HPCs,
    199 		 * but we can also actually probe for HPCs.
    200 		 * Assume at least one.
    201 		 */
    202 		for (sc->dwlpx_nhpc = 1; sc->dwlpx_nhpc < NHPC;
    203 		    sc->dwlpx_nhpc++) {
    204 			if (badaddr(KV(PCIA_CTL(sc->dwlpx_nhpc) + ls),
    205 			    sizeof (ctl)) != 0) {
    206 				break;
    207 			}
    208 		}
    209 		if (sc->dwlpx_nhpc != NHPC) {
    210 			/* clear (potential) Illegal CSR Address Error */
    211 			REGVAL(PCIA_ERR(0) + DWLPX_SYSBASE(sc)) =
    212 				PCIA_ERR_ALLERR;
    213 		}
    214 
    215 		dwlpx_bus_io_init(&ccp->cc_iot, ccp);
    216 		dwlpx_bus_mem_init(&ccp->cc_memt, ccp);
    217 	}
    218 	dwlpx_pci_init(&ccp->cc_pc, ccp);
    219 	ccp->cc_sc = sc;
    220 
    221 	/*
    222 	 * Establish a precalculated base for convenience's sake.
    223 	 */
    224 	ccp->cc_sysbase = ls;
    225 
    226 	/*
    227 	 * If there are only 2 HPCs, then the 'present' register is not
    228 	 * implemented, so there will only ever be 32K SG entries. Otherwise
    229 	 * any revision greater than zero will have 128K entries.
    230 	 */
    231 	ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase);
    232 	if (sc->dwlpx_nhpc == 2) {
    233 		sc->dwlpx_sgmapsz = DWLPX_SG32K;
    234 #if 0
    235 	/*
    236 	 * As of 2/25/98- When I enable SG128K, and then have to flip
    237 	 * TBIT below, I get bad SGRAM errors. We'll fix this later
    238 	 * if this gets important.
    239 	 */
    240 	} else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
    241 		sc->dwlpx_sgmapsz = DWLPX_SG128K;
    242 #endif
    243 	} else {
    244 		sc->dwlpx_sgmapsz = DWLPX_SG32K;
    245 	}
    246 
    247 	/*
    248 	 * Set up interrupt stuff for this DWLPX.
    249 	 *
    250 	 * Note that all PCI interrupt pins are disabled at this time.
    251 	 *
    252 	 * Do this even for all HPCs- even for the nonexistent
    253 	 * one on hose zero of a KFTIA.
    254 	 */
    255 	mutex_enter(&cpu_lock);
    256 	vec = scb_alloc(dwlpx_errintr, sc);
    257 	mutex_exit(&cpu_lock);
    258 	if (vec == SCB_ALLOC_FAILED)
    259 		panic("%s: unable to allocate error vector",
    260 		    device_xname(sc->dwlpx_dev));
    261 	aprint_normal_dev(sc->dwlpx_dev, "error interrupt at vector 0x%lx\n",
    262 	    vec);
    263 	for (i = 0; i < NHPC; i++) {
    264 		REGVAL(PCIA_IMASK(i) + ccp->cc_sysbase) = DWLPX_IMASK_DFLT;
    265 		REGVAL(PCIA_ERRVEC(i) + ccp->cc_sysbase) = vec;
    266 	}
    267 
    268 	/*
    269 	 * Establish HAE values, as well as make sure of sanity elsewhere.
    270 	 */
    271 	for (i = 0; i < sc->dwlpx_nhpc; i++) {
    272 		ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase);
    273 		ctl &= 0x0fffffff;
    274 		ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
    275 		/*
    276 		 * I originally also had it or'ing in 3, which makes no sense.
    277 		 */
    278 
    279 		ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB;
    280 
    281 		/*
    282 		 * Only valid if we're attached to a KFTIA or a KTHA.
    283 		 */
    284 		ctl |= PCIA_CTL_3UP;
    285 
    286 		ctl |= PCIA_CTL_CUTENA;
    287 
    288 		/*
    289 		 * Fit in appropriate S/G Map Ram size.
    290 		 */
    291 		if (sc->dwlpx_sgmapsz == DWLPX_SG32K)
    292 			ctl |= PCIA_CTL_SG32K;
    293 		else if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
    294 			ctl |= PCIA_CTL_SG128K;
    295 		else
    296 			ctl |= PCIA_CTL_SG32K;
    297 
    298 		REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl;
    299 	}
    300 	/*
    301 	 * Enable TBIT if required
    302 	 */
    303 	if (sc->dwlpx_sgmapsz == DWLPX_SG128K)
    304 		REGVAL(PCIA_TBIT + ccp->cc_sysbase) = 1;
    305 	alpha_mb();
    306 	ccp->cc_initted = 1;
    307 }
    308 
    309 void
    310 dwlpx_errintr(void *arg, unsigned long vec)
    311 {
    312 	struct dwlpx_softc *sc = arg;
    313 	struct dwlpx_config *ccp = &sc->dwlpx_cc;
    314 	int i;
    315 	struct {
    316 		uint32_t err;
    317 		uint32_t addr;
    318 	} hpcs[NHPC];
    319 
    320 	for (i = 0; i < sc->dwlpx_nhpc; i++) {
    321 		hpcs[i].err = REGVAL(PCIA_ERR(i) + ccp->cc_sysbase);
    322 		hpcs[i].addr = REGVAL(PCIA_FADR(i) + ccp->cc_sysbase);
    323 	}
    324 	aprint_error_dev(sc->dwlpx_dev, "node %d hose %d error interrupt\n",
    325 	    sc->dwlpx_node, sc->dwlpx_hosenum);
    326 
    327 	for (i = 0; i < sc->dwlpx_nhpc; i++) {
    328 		if ((hpcs[i].err & PCIA_ERR_ERROR) == 0)
    329 			continue;
    330 		aprint_error("\tHPC %d: ERR=0x%08x; DMA %s Memory, "
    331 			"Failing Address 0x%x\n",
    332 			i, hpcs[i].err, hpcs[i].addr & 0x1? "write to" :
    333 			"read from", hpcs[i].addr & ~3);
    334 		if (hpcs[i].err & PCIA_ERR_SERR_L)
    335 			aprint_error("\t       PCI device asserted SERR_L\n");
    336 		if (hpcs[i].err & PCIA_ERR_ILAT)
    337 			aprint_error("\t       Incremental Latency Exceeded\n");
    338 		if (hpcs[i].err & PCIA_ERR_SGPRTY)
    339 			aprint_error("\t       CPU access of SG RAM Parity Error\n");
    340 		if (hpcs[i].err & PCIA_ERR_ILLCSR)
    341 			aprint_error("\t       Illegal CSR Address Error\n");
    342 		if (hpcs[i].err & PCIA_ERR_PCINXM)
    343 			aprint_error("\t       Nonexistent PCI Address Error\n");
    344 		if (hpcs[i].err & PCIA_ERR_DSCERR)
    345 			aprint_error("\t       PCI Target Disconnect Error\n");
    346 		if (hpcs[i].err & PCIA_ERR_ABRT)
    347 			aprint_error("\t       PCI Target Abort Error\n");
    348 		if (hpcs[i].err & PCIA_ERR_WPRTY)
    349 			aprint_error("\t       PCI Write Parity Error\n");
    350 		if (hpcs[i].err & PCIA_ERR_DPERR)
    351 			aprint_error("\t       PCI Data Parity Error\n");
    352 		if (hpcs[i].err & PCIA_ERR_APERR)
    353 			aprint_error("\t       PCI Address Parity Error\n");
    354 		if (hpcs[i].err & PCIA_ERR_DFLT)
    355 			aprint_error("\t       SG Map RAM Invalid Entry Error\n");
    356 		if (hpcs[i].err & PCIA_ERR_DPRTY)
    357 			aprint_error("\t       DMA access of SG RAM Parity Error\n");
    358 		if (hpcs[i].err & PCIA_ERR_DRPERR)
    359 			aprint_error("\t       DMA Read Return Parity Error\n");
    360 		if (hpcs[i].err & PCIA_ERR_MABRT)
    361 			aprint_error("\t       PCI Master Abort Error\n");
    362 		if (hpcs[i].err & PCIA_ERR_CPRTY)
    363 			aprint_error("\t       CSR Parity Error\n");
    364 		if (hpcs[i].err & PCIA_ERR_COVR)
    365 			aprint_error("\t       CSR Overrun Error\n");
    366 		if (hpcs[i].err & PCIA_ERR_MBPERR)
    367 			aprint_error("\t       Mailbox Parity Error\n");
    368 		if (hpcs[i].err & PCIA_ERR_MBILI)
    369 			aprint_error("\t       Mailbox Illegal Length Error\n");
    370 		REGVAL(PCIA_ERR(i) + ccp->cc_sysbase) = hpcs[i].err;
    371 	}
    372 }
    373