dwlpx_pci.c revision 1.1
1 /* $NetBSD: dwlpx_pci.c,v 1.1 1997/03/12 19:20:02 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1997 5 * Matthew Jacob 6 * NASA AMES Research Center. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice immediately at the beginning of the file, without modification, 14 * this list of conditions, and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/device.h> 38 #include <vm/vm.h> 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <alpha/tlsb/tlsbreg.h> 43 #include <alpha/pci/dwlpxreg.h> 44 #include <alpha/pci/dwlpxvar.h> 45 46 /* #define DO_SECONDARIES 1 */ 47 48 #define KV(_addr) ((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr))) 49 50 void dwlpx_attach_hook __P((struct device *, struct device *, 51 struct pcibus_attach_args *)); 52 int dwlpx_bus_maxdevs __P((void *, int)); 53 pcitag_t dwlpx_make_tag __P((void *, int, int, int)); 54 void dwlpx_decompose_tag __P((void *, pcitag_t, int *, int *, 55 int *)); 56 pcireg_t dwlpx_conf_read __P((void *, pcitag_t, int)); 57 void dwlpx_conf_write __P((void *, pcitag_t, int, pcireg_t)); 58 59 void 60 dwlpx_pci_init(pc, v) 61 pci_chipset_tag_t pc; 62 void *v; 63 { 64 pc->pc_conf_v = v; 65 pc->pc_attach_hook = dwlpx_attach_hook; 66 pc->pc_bus_maxdevs = dwlpx_bus_maxdevs; 67 pc->pc_make_tag = dwlpx_make_tag; 68 pc->pc_decompose_tag = dwlpx_decompose_tag; 69 pc->pc_conf_read = dwlpx_conf_read; 70 pc->pc_conf_write = dwlpx_conf_write; 71 } 72 73 void 74 dwlpx_attach_hook(parent, self, pba) 75 struct device *parent, *self; 76 struct pcibus_attach_args *pba; 77 { 78 #if 0 79 struct dwlpx_config *ccp = pba->pba_pc->pc_conf_v; 80 printf("dwlpx_attach_hook for %s\n", ccp->cc_sc->dwlpx_dev.dv_xname); 81 #endif 82 } 83 84 int 85 dwlpx_bus_maxdevs(cpv, busno) 86 void *cpv; 87 int busno; 88 { 89 return DWLPX_MAXDEV; 90 } 91 92 pcitag_t 93 dwlpx_make_tag(cpv, b, d, f) 94 void *cpv; 95 int b, d, f; 96 { 97 pcitag_t tag; 98 int hpcdev, pci_idsel; 99 100 pci_idsel = (1 << ((d & 0x3) + 2)); 101 hpcdev = d >> 2; 102 tag = (b << 24) | (hpcdev << 22) | (pci_idsel << 16) | (f << 13); 103 return (tag); 104 } 105 106 void 107 dwlpx_decompose_tag(cpv, tag, bp, dp, fp) 108 void *cpv; 109 pcitag_t tag; 110 int *bp, *dp, *fp; 111 { 112 113 if (bp != NULL) 114 *bp = (tag >> 24) & 0xff; 115 if (dp != NULL) { 116 int j, i = (tag >> 18) & 0xf; 117 j = -1; 118 while (i != 0) { 119 j++; 120 i >>= 1; 121 } 122 j += (((tag >> 22) & 3) << 2); 123 *dp = j; 124 } 125 if (fp != NULL) 126 *fp = (tag >> 13) & 0x7; 127 } 128 129 pcireg_t 130 dwlpx_conf_read(cpv, tag, offset) 131 void *cpv; 132 pcitag_t tag; 133 int offset; 134 { 135 struct dwlpx_config *ccp = cpv; 136 struct dwlpx_softc *sc; 137 pcireg_t *dp, data = (pcireg_t) -1; 138 unsigned long paddr; 139 int secondary, i, s = 0; 140 u_int32_t rvp; 141 142 if (ccp == NULL) { 143 panic("NULL ccp in dwlpx_conf_read\n"); 144 } 145 sc = ccp->cc_sc; 146 secondary = tag >> 24; 147 if (secondary) { 148 #ifdef DO_SECONDARIES 149 tag &= 0x1fffff; 150 tag |= (secondary << 21); 151 152 printf("read secondary %d reg %x (tag %x)", 153 secondary, offset, tag); 154 #if 0 155 #endif 156 157 alpha_pal_draina(); 158 s = splhigh(); 159 /* 160 * Set up HPCs for type 1 cycles. 161 */ 162 for (i = 0; i < sc->dwlpx_nhpc; i++) { 163 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 1; 164 alpha_mb(); 165 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 166 alpha_mb(); 167 } 168 #else 169 return (data); 170 #endif 171 } 172 paddr = (unsigned long) tag; 173 paddr |= DWLPX_PCI_CONF; 174 paddr |= ((unsigned long) ((offset >> 2) << 7)); 175 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 176 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 177 paddr |= (1LL << 39); 178 179 dp = (pcireg_t *)KV(paddr); 180 if (badaddr(dp, sizeof (*dp)) == 0) { 181 data = *dp; 182 } 183 if (secondary) { 184 alpha_pal_draina(); 185 for (i = 0; i < sc->dwlpx_nhpc; i++) { 186 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & ~1; 187 alpha_mb(); 188 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 189 alpha_mb(); 190 } 191 (void) splx(s); 192 #ifdef DO_SECONDARIES 193 printf("=%x\n", data); 194 #if 0 195 #endif 196 #endif 197 } 198 return (data); 199 } 200 201 void 202 dwlpx_conf_write(cpv, tag, offset, data) 203 void *cpv; 204 pcitag_t tag; 205 int offset; 206 pcireg_t data; 207 { 208 struct dwlpx_config *ccp = cpv; 209 struct dwlpx_softc *sc; 210 pcireg_t *dp; 211 unsigned long paddr; 212 int secondary, i, s = 0; 213 u_int32_t rvp; 214 215 if (ccp == NULL) { 216 panic("NULL ccp in dwlpx_conf_write\n"); 217 } 218 sc = ccp->cc_sc; 219 secondary = tag >> 24; 220 if (secondary) { 221 tag &= 0x1fffff; 222 tag |= (secondary << 21); 223 printf("write secondary %d reg %x (tag %x) with %x\n", 224 secondary, offset, tag, data); 225 #if 0 226 #endif 227 228 alpha_pal_draina(); 229 s = splhigh(); 230 /* 231 * Set up HPCs for type 1 cycles. 232 */ 233 for (i = 0; i < sc->dwlpx_nhpc; i++) { 234 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 1; 235 alpha_mb(); 236 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 237 alpha_mb(); 238 } 239 } 240 paddr = (unsigned long) tag; 241 paddr |= DWLPX_PCI_CONF; 242 paddr |= ((unsigned long) ((offset >> 2) << 7)); 243 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 244 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 245 paddr |= (1LL << 39); 246 247 dp = (pcireg_t *)KV(paddr); 248 *dp = data; 249 alpha_mb(); 250 if (secondary) { 251 alpha_pal_draina(); 252 for (i = 0; i < sc->dwlpx_nhpc; i++) { 253 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & ~1; 254 alpha_mb(); 255 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 256 alpha_mb(); 257 } 258 (void) splx(s); 259 } 260 } 261
Indexes created Fri Sep 26 08:10:20 GMT 2025