dwlpx_pci.c revision 1.13
1 /* $NetBSD: dwlpx_pci.c,v 1.13 2009/03/14 14:45:53 dsl Exp $ */ 2 3 /* 4 * Copyright (c) 1997 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: dwlpx_pci.c,v 1.13 2009/03/14 14:45:53 dsl Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <alpha/tlsb/tlsbreg.h> 47 #include <alpha/pci/dwlpxreg.h> 48 #include <alpha/pci/dwlpxvar.h> 49 50 #define KV(_addr) ((void *)ALPHA_PHYS_TO_K0SEG((_addr))) 51 52 void dwlpx_attach_hook(struct device *, struct device *, 53 struct pcibus_attach_args *); 54 int dwlpx_bus_maxdevs(void *, int); 55 pcitag_t dwlpx_make_tag(void *, int, int, int); 56 void dwlpx_decompose_tag(void *, pcitag_t, int *, int *, 57 int *); 58 pcireg_t dwlpx_conf_read(void *, pcitag_t, int); 59 void dwlpx_conf_write(void *, pcitag_t, int, pcireg_t); 60 61 void 62 dwlpx_pci_init(pc, v) 63 pci_chipset_tag_t pc; 64 void *v; 65 { 66 pc->pc_conf_v = v; 67 pc->pc_attach_hook = dwlpx_attach_hook; 68 pc->pc_bus_maxdevs = dwlpx_bus_maxdevs; 69 pc->pc_make_tag = dwlpx_make_tag; 70 pc->pc_decompose_tag = dwlpx_decompose_tag; 71 pc->pc_conf_read = dwlpx_conf_read; 72 pc->pc_conf_write = dwlpx_conf_write; 73 } 74 75 void 76 dwlpx_attach_hook(parent, self, pba) 77 struct device *parent, *self; 78 struct pcibus_attach_args *pba; 79 { 80 #if 0 81 struct dwlpx_config *ccp = pba->pba_pc->pc_conf_v; 82 printf("dwlpx_attach_hook for %s\n", ccp->cc_sc->dwlpx_dev.dv_xname); 83 #endif 84 } 85 86 int 87 dwlpx_bus_maxdevs(cpv, busno) 88 void *cpv; 89 int busno; 90 { 91 return DWLPX_MAXDEV; 92 } 93 94 pcitag_t 95 dwlpx_make_tag(cpv, b, d, f) 96 void *cpv; 97 int b, d, f; 98 { 99 pcitag_t tag; 100 int hpcdev, pci_idsel; 101 102 pci_idsel = (1 << ((d & 0x3) + 2)); 103 hpcdev = d >> 2; 104 tag = (b << 24) | (hpcdev << 22) | (pci_idsel << 16) | (f << 13); 105 return (tag); 106 } 107 108 void 109 dwlpx_decompose_tag(cpv, tag, bp, dp, fp) 110 void *cpv; 111 pcitag_t tag; 112 int *bp, *dp, *fp; 113 { 114 115 if (bp != NULL) 116 *bp = (tag >> 24) & 0xff; 117 if (dp != NULL) { 118 int j, i = (tag >> 18) & 0xf; 119 j = -1; 120 while (i != 0) { 121 j++; 122 i >>= 1; 123 } 124 j += (((tag >> 22) & 3) << 2); 125 *dp = j; 126 } 127 if (fp != NULL) 128 *fp = (tag >> 13) & 0x7; 129 } 130 131 pcireg_t 132 dwlpx_conf_read(cpv, tag, offset) 133 void *cpv; 134 pcitag_t tag; 135 int offset; 136 { 137 struct dwlpx_config *ccp = cpv; 138 struct dwlpx_softc *sc; 139 pcireg_t *dp, data = (pcireg_t) -1; 140 unsigned long paddr; 141 int secondary, i, s = 0; 142 u_int32_t rvp; 143 144 if (ccp == NULL) { 145 panic("NULL ccp in dwlpx_conf_read"); 146 } 147 sc = ccp->cc_sc; 148 secondary = tag >> 24; 149 if (secondary) { 150 tag &= 0x1fffff; 151 tag |= (secondary << 21); 152 153 #if 0 154 printf("read secondary %d reg %x (tag %x)", 155 secondary, offset, tag); 156 #endif 157 158 alpha_pal_draina(); 159 s = splhigh(); 160 /* 161 * Set up HPCs for type 1 cycles. 162 */ 163 for (i = 0; i < sc->dwlpx_nhpc; i++) { 164 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 165 PCIA_CTL_T1CYC; 166 alpha_mb(); 167 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 168 alpha_mb(); 169 } 170 } 171 paddr = (unsigned long) tag; 172 paddr |= DWLPX_PCI_CONF; 173 paddr |= ((unsigned long) ((offset >> 2) << 7)); 174 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 175 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 176 paddr |= (1LL << 39); 177 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */ 178 179 dp = (pcireg_t *)KV(paddr); 180 if (badaddr(dp, sizeof (*dp)) == 0) { 181 data = *dp; 182 } 183 if (secondary) { 184 alpha_pal_draina(); 185 for (i = 0; i < sc->dwlpx_nhpc; i++) { 186 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & 187 ~PCIA_CTL_T1CYC; 188 alpha_mb(); 189 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 190 alpha_mb(); 191 } 192 (void) splx(s); 193 #if 0 194 printf("=%x\n", data); 195 #endif 196 } 197 return (data); 198 } 199 200 void 201 dwlpx_conf_write(cpv, tag, offset, data) 202 void *cpv; 203 pcitag_t tag; 204 int offset; 205 pcireg_t data; 206 { 207 struct dwlpx_config *ccp = cpv; 208 struct dwlpx_softc *sc; 209 pcireg_t *dp; 210 unsigned long paddr; 211 int secondary, i, s = 0; 212 u_int32_t rvp; 213 214 if (ccp == NULL) { 215 panic("NULL ccp in dwlpx_conf_write"); 216 } 217 sc = ccp->cc_sc; 218 secondary = tag >> 24; 219 if (secondary) { 220 tag &= 0x1fffff; 221 tag |= (secondary << 21); 222 #if 0 223 printf("write secondary %d reg %x (tag %x) with %x\n", 224 secondary, offset, tag, data); 225 #endif 226 227 alpha_pal_draina(); 228 s = splhigh(); 229 /* 230 * Set up HPCs for type 1 cycles. 231 */ 232 for (i = 0; i < sc->dwlpx_nhpc; i++) { 233 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 234 PCIA_CTL_T1CYC; 235 alpha_mb(); 236 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 237 alpha_mb(); 238 } 239 } 240 paddr = (unsigned long) tag; 241 paddr |= DWLPX_PCI_CONF; 242 paddr |= ((unsigned long) ((offset >> 2) << 7)); 243 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 244 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 245 paddr |= (1LL << 39); 246 paddr |= (3LL << 3); /* 32 bit PCI byte enables */ 247 248 dp = (pcireg_t *)KV(paddr); 249 *dp = data; 250 alpha_mb(); 251 if (secondary) { 252 alpha_pal_draina(); 253 for (i = 0; i < sc->dwlpx_nhpc; i++) { 254 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & 255 ~PCIA_CTL_T1CYC; 256 alpha_mb(); 257 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 258 alpha_mb(); 259 } 260 (void) splx(s); 261 } 262 } 263
Indexes created Fri Sep 26 20:09:58 GMT 2025