dwlpx_pci.c revision 1.14
1 /* $NetBSD: dwlpx_pci.c,v 1.14 2009/03/14 15:35:59 dsl Exp $ */ 2 3 /* 4 * Copyright (c) 1997 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: dwlpx_pci.c,v 1.14 2009/03/14 15:35:59 dsl Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <alpha/tlsb/tlsbreg.h> 47 #include <alpha/pci/dwlpxreg.h> 48 #include <alpha/pci/dwlpxvar.h> 49 50 #define KV(_addr) ((void *)ALPHA_PHYS_TO_K0SEG((_addr))) 51 52 void dwlpx_attach_hook(struct device *, struct device *, 53 struct pcibus_attach_args *); 54 int dwlpx_bus_maxdevs(void *, int); 55 pcitag_t dwlpx_make_tag(void *, int, int, int); 56 void dwlpx_decompose_tag(void *, pcitag_t, int *, int *, 57 int *); 58 pcireg_t dwlpx_conf_read(void *, pcitag_t, int); 59 void dwlpx_conf_write(void *, pcitag_t, int, pcireg_t); 60 61 void 62 dwlpx_pci_init(pci_chipset_tag_t pc, void *v) 63 { 64 pc->pc_conf_v = v; 65 pc->pc_attach_hook = dwlpx_attach_hook; 66 pc->pc_bus_maxdevs = dwlpx_bus_maxdevs; 67 pc->pc_make_tag = dwlpx_make_tag; 68 pc->pc_decompose_tag = dwlpx_decompose_tag; 69 pc->pc_conf_read = dwlpx_conf_read; 70 pc->pc_conf_write = dwlpx_conf_write; 71 } 72 73 void 74 dwlpx_attach_hook(parent, self, pba) 75 struct device *parent, *self; 76 struct pcibus_attach_args *pba; 77 { 78 #if 0 79 struct dwlpx_config *ccp = pba->pba_pc->pc_conf_v; 80 printf("dwlpx_attach_hook for %s\n", ccp->cc_sc->dwlpx_dev.dv_xname); 81 #endif 82 } 83 84 int 85 dwlpx_bus_maxdevs(void *cpv, int busno) 86 { 87 return DWLPX_MAXDEV; 88 } 89 90 pcitag_t 91 dwlpx_make_tag(cpv, b, d, f) 92 void *cpv; 93 int b, d, f; 94 { 95 pcitag_t tag; 96 int hpcdev, pci_idsel; 97 98 pci_idsel = (1 << ((d & 0x3) + 2)); 99 hpcdev = d >> 2; 100 tag = (b << 24) | (hpcdev << 22) | (pci_idsel << 16) | (f << 13); 101 return (tag); 102 } 103 104 void 105 dwlpx_decompose_tag(cpv, tag, bp, dp, fp) 106 void *cpv; 107 pcitag_t tag; 108 int *bp, *dp, *fp; 109 { 110 111 if (bp != NULL) 112 *bp = (tag >> 24) & 0xff; 113 if (dp != NULL) { 114 int j, i = (tag >> 18) & 0xf; 115 j = -1; 116 while (i != 0) { 117 j++; 118 i >>= 1; 119 } 120 j += (((tag >> 22) & 3) << 2); 121 *dp = j; 122 } 123 if (fp != NULL) 124 *fp = (tag >> 13) & 0x7; 125 } 126 127 pcireg_t 128 dwlpx_conf_read(void *cpv, pcitag_t tag, int offset) 129 { 130 struct dwlpx_config *ccp = cpv; 131 struct dwlpx_softc *sc; 132 pcireg_t *dp, data = (pcireg_t) -1; 133 unsigned long paddr; 134 int secondary, i, s = 0; 135 u_int32_t rvp; 136 137 if (ccp == NULL) { 138 panic("NULL ccp in dwlpx_conf_read"); 139 } 140 sc = ccp->cc_sc; 141 secondary = tag >> 24; 142 if (secondary) { 143 tag &= 0x1fffff; 144 tag |= (secondary << 21); 145 146 #if 0 147 printf("read secondary %d reg %x (tag %x)", 148 secondary, offset, tag); 149 #endif 150 151 alpha_pal_draina(); 152 s = splhigh(); 153 /* 154 * Set up HPCs for type 1 cycles. 155 */ 156 for (i = 0; i < sc->dwlpx_nhpc; i++) { 157 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 158 PCIA_CTL_T1CYC; 159 alpha_mb(); 160 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 161 alpha_mb(); 162 } 163 } 164 paddr = (unsigned long) tag; 165 paddr |= DWLPX_PCI_CONF; 166 paddr |= ((unsigned long) ((offset >> 2) << 7)); 167 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 168 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 169 paddr |= (1LL << 39); 170 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */ 171 172 dp = (pcireg_t *)KV(paddr); 173 if (badaddr(dp, sizeof (*dp)) == 0) { 174 data = *dp; 175 } 176 if (secondary) { 177 alpha_pal_draina(); 178 for (i = 0; i < sc->dwlpx_nhpc; i++) { 179 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & 180 ~PCIA_CTL_T1CYC; 181 alpha_mb(); 182 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 183 alpha_mb(); 184 } 185 (void) splx(s); 186 #if 0 187 printf("=%x\n", data); 188 #endif 189 } 190 return (data); 191 } 192 193 void 194 dwlpx_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data) 195 { 196 struct dwlpx_config *ccp = cpv; 197 struct dwlpx_softc *sc; 198 pcireg_t *dp; 199 unsigned long paddr; 200 int secondary, i, s = 0; 201 u_int32_t rvp; 202 203 if (ccp == NULL) { 204 panic("NULL ccp in dwlpx_conf_write"); 205 } 206 sc = ccp->cc_sc; 207 secondary = tag >> 24; 208 if (secondary) { 209 tag &= 0x1fffff; 210 tag |= (secondary << 21); 211 #if 0 212 printf("write secondary %d reg %x (tag %x) with %x\n", 213 secondary, offset, tag, data); 214 #endif 215 216 alpha_pal_draina(); 217 s = splhigh(); 218 /* 219 * Set up HPCs for type 1 cycles. 220 */ 221 for (i = 0; i < sc->dwlpx_nhpc; i++) { 222 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 223 PCIA_CTL_T1CYC; 224 alpha_mb(); 225 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 226 alpha_mb(); 227 } 228 } 229 paddr = (unsigned long) tag; 230 paddr |= DWLPX_PCI_CONF; 231 paddr |= ((unsigned long) ((offset >> 2) << 7)); 232 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 233 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 234 paddr |= (1LL << 39); 235 paddr |= (3LL << 3); /* 32 bit PCI byte enables */ 236 237 dp = (pcireg_t *)KV(paddr); 238 *dp = data; 239 alpha_mb(); 240 if (secondary) { 241 alpha_pal_draina(); 242 for (i = 0; i < sc->dwlpx_nhpc; i++) { 243 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & 244 ~PCIA_CTL_T1CYC; 245 alpha_mb(); 246 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 247 alpha_mb(); 248 } 249 (void) splx(s); 250 } 251 } 252
Indexes created Fri Sep 26 08:10:20 GMT 2025