dwlpx_pci.c revision 1.4
1 /* $NetBSD: dwlpx_pci.c,v 1.4 1997/03/15 03:15:20 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1997 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <vm/vm.h> 38 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 #include <alpha/tlsb/tlsbreg.h> 42 #include <alpha/pci/dwlpxreg.h> 43 #include <alpha/pci/dwlpxvar.h> 44 45 #define DO_SECONDARIES 1 46 47 #define KV(_addr) ((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr))) 48 49 void dwlpx_attach_hook __P((struct device *, struct device *, 50 struct pcibus_attach_args *)); 51 int dwlpx_bus_maxdevs __P((void *, int)); 52 pcitag_t dwlpx_make_tag __P((void *, int, int, int)); 53 void dwlpx_decompose_tag __P((void *, pcitag_t, int *, int *, 54 int *)); 55 pcireg_t dwlpx_conf_read __P((void *, pcitag_t, int)); 56 void dwlpx_conf_write __P((void *, pcitag_t, int, pcireg_t)); 57 58 void 59 dwlpx_pci_init(pc, v) 60 pci_chipset_tag_t pc; 61 void *v; 62 { 63 pc->pc_conf_v = v; 64 pc->pc_attach_hook = dwlpx_attach_hook; 65 pc->pc_bus_maxdevs = dwlpx_bus_maxdevs; 66 pc->pc_make_tag = dwlpx_make_tag; 67 pc->pc_decompose_tag = dwlpx_decompose_tag; 68 pc->pc_conf_read = dwlpx_conf_read; 69 pc->pc_conf_write = dwlpx_conf_write; 70 } 71 72 void 73 dwlpx_attach_hook(parent, self, pba) 74 struct device *parent, *self; 75 struct pcibus_attach_args *pba; 76 { 77 #if 0 78 struct dwlpx_config *ccp = pba->pba_pc->pc_conf_v; 79 printf("dwlpx_attach_hook for %s\n", ccp->cc_sc->dwlpx_dev.dv_xname); 80 #endif 81 } 82 83 int 84 dwlpx_bus_maxdevs(cpv, busno) 85 void *cpv; 86 int busno; 87 { 88 return DWLPX_MAXDEV; 89 } 90 91 pcitag_t 92 dwlpx_make_tag(cpv, b, d, f) 93 void *cpv; 94 int b, d, f; 95 { 96 pcitag_t tag; 97 int hpcdev, pci_idsel; 98 99 pci_idsel = (1 << ((d & 0x3) + 2)); 100 hpcdev = d >> 2; 101 tag = (b << 24) | (hpcdev << 22) | (pci_idsel << 16) | (f << 13); 102 return (tag); 103 } 104 105 void 106 dwlpx_decompose_tag(cpv, tag, bp, dp, fp) 107 void *cpv; 108 pcitag_t tag; 109 int *bp, *dp, *fp; 110 { 111 112 if (bp != NULL) 113 *bp = (tag >> 24) & 0xff; 114 if (dp != NULL) { 115 int j, i = (tag >> 18) & 0xf; 116 j = -1; 117 while (i != 0) { 118 j++; 119 i >>= 1; 120 } 121 j += (((tag >> 22) & 3) << 2); 122 *dp = j; 123 } 124 if (fp != NULL) 125 *fp = (tag >> 13) & 0x7; 126 } 127 128 pcireg_t 129 dwlpx_conf_read(cpv, tag, offset) 130 void *cpv; 131 pcitag_t tag; 132 int offset; 133 { 134 struct dwlpx_config *ccp = cpv; 135 struct dwlpx_softc *sc; 136 pcireg_t *dp, data = (pcireg_t) -1; 137 unsigned long paddr; 138 int secondary, i, s = 0; 139 u_int32_t rvp; 140 141 if (ccp == NULL) { 142 panic("NULL ccp in dwlpx_conf_read\n"); 143 } 144 sc = ccp->cc_sc; 145 secondary = tag >> 24; 146 if (secondary) { 147 #ifdef DO_SECONDARIES 148 tag &= 0x1fffff; 149 tag |= (secondary << 21); 150 151 #if 0 152 printf("read secondary %d reg %x (tag %x)", 153 secondary, offset, tag); 154 #endif 155 156 alpha_pal_draina(); 157 s = splhigh(); 158 /* 159 * Set up HPCs for type 1 cycles. 160 */ 161 for (i = 0; i < sc->dwlpx_nhpc; i++) { 162 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 1; 163 alpha_mb(); 164 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 165 alpha_mb(); 166 } 167 #else 168 return (data); 169 #endif 170 } 171 paddr = (unsigned long) tag; 172 paddr |= DWLPX_PCI_CONF; 173 paddr |= ((unsigned long) ((offset >> 2) << 7)); 174 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 175 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 176 paddr |= (1LL << 39); 177 paddr |= (1LL << 3); /* 32 Bit PCI byte enables */ 178 179 dp = (pcireg_t *)KV(paddr); 180 if (badaddr(dp, sizeof (*dp)) == 0) { 181 data = *dp; 182 } 183 if (secondary) { 184 alpha_pal_draina(); 185 for (i = 0; i < sc->dwlpx_nhpc; i++) { 186 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & ~1; 187 alpha_mb(); 188 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 189 alpha_mb(); 190 } 191 (void) splx(s); 192 #ifdef DO_SECONDARIES 193 #if 0 194 printf("=%x\n", data); 195 #endif 196 #endif 197 } 198 return (data); 199 } 200 201 void 202 dwlpx_conf_write(cpv, tag, offset, data) 203 void *cpv; 204 pcitag_t tag; 205 int offset; 206 pcireg_t data; 207 { 208 struct dwlpx_config *ccp = cpv; 209 struct dwlpx_softc *sc; 210 pcireg_t *dp; 211 unsigned long paddr; 212 int secondary, i, s = 0; 213 u_int32_t rvp; 214 215 if (ccp == NULL) { 216 panic("NULL ccp in dwlpx_conf_write\n"); 217 } 218 sc = ccp->cc_sc; 219 secondary = tag >> 24; 220 if (secondary) { 221 tag &= 0x1fffff; 222 tag |= (secondary << 21); 223 #if 0 224 printf("write secondary %d reg %x (tag %x) with %x\n", 225 secondary, offset, tag, data); 226 #endif 227 228 alpha_pal_draina(); 229 s = splhigh(); 230 /* 231 * Set up HPCs for type 1 cycles. 232 */ 233 for (i = 0; i < sc->dwlpx_nhpc; i++) { 234 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 1; 235 alpha_mb(); 236 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 237 alpha_mb(); 238 } 239 } 240 paddr = (unsigned long) tag; 241 paddr |= DWLPX_PCI_CONF; 242 paddr |= ((unsigned long) ((offset >> 2) << 7)); 243 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 244 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 245 paddr |= (1LL << 39); 246 paddr |= (1LL << 3); /* 32 bit PCI byte enables */ 247 248 dp = (pcireg_t *)KV(paddr); 249 *dp = data; 250 alpha_mb(); 251 if (secondary) { 252 alpha_pal_draina(); 253 for (i = 0; i < sc->dwlpx_nhpc; i++) { 254 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & ~1; 255 alpha_mb(); 256 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 257 alpha_mb(); 258 } 259 (void) splx(s); 260 } 261 } 262
Indexes created Fri Sep 26 20:09:58 GMT 2025