dwlpx_pci.c revision 1.9
1 /* $NetBSD: dwlpx_pci.c,v 1.9 1998/04/15 00:48:58 mjacob Exp $ */ 2 3 /* 4 * Copyright (c) 1997 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: dwlpx_pci.c,v 1.9 1998/04/15 00:48:58 mjacob Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <vm/vm.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <alpha/tlsb/tlsbreg.h> 46 #include <alpha/pci/dwlpxreg.h> 47 #include <alpha/pci/dwlpxvar.h> 48 49 #define KV(_addr) ((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr))) 50 51 void dwlpx_attach_hook __P((struct device *, struct device *, 52 struct pcibus_attach_args *)); 53 int dwlpx_bus_maxdevs __P((void *, int)); 54 pcitag_t dwlpx_make_tag __P((void *, int, int, int)); 55 void dwlpx_decompose_tag __P((void *, pcitag_t, int *, int *, 56 int *)); 57 pcireg_t dwlpx_conf_read __P((void *, pcitag_t, int)); 58 void dwlpx_conf_write __P((void *, pcitag_t, int, pcireg_t)); 59 60 void 61 dwlpx_pci_init(pc, v) 62 pci_chipset_tag_t pc; 63 void *v; 64 { 65 pc->pc_conf_v = v; 66 pc->pc_attach_hook = dwlpx_attach_hook; 67 pc->pc_bus_maxdevs = dwlpx_bus_maxdevs; 68 pc->pc_make_tag = dwlpx_make_tag; 69 pc->pc_decompose_tag = dwlpx_decompose_tag; 70 pc->pc_conf_read = dwlpx_conf_read; 71 pc->pc_conf_write = dwlpx_conf_write; 72 } 73 74 void 75 dwlpx_attach_hook(parent, self, pba) 76 struct device *parent, *self; 77 struct pcibus_attach_args *pba; 78 { 79 #if 0 80 struct dwlpx_config *ccp = pba->pba_pc->pc_conf_v; 81 printf("dwlpx_attach_hook for %s\n", ccp->cc_sc->dwlpx_dev.dv_xname); 82 #endif 83 } 84 85 int 86 dwlpx_bus_maxdevs(cpv, busno) 87 void *cpv; 88 int busno; 89 { 90 return DWLPX_MAXDEV; 91 } 92 93 pcitag_t 94 dwlpx_make_tag(cpv, b, d, f) 95 void *cpv; 96 int b, d, f; 97 { 98 pcitag_t tag; 99 int hpcdev, pci_idsel; 100 101 pci_idsel = (1 << ((d & 0x3) + 2)); 102 hpcdev = d >> 2; 103 tag = (b << 24) | (hpcdev << 22) | (pci_idsel << 16) | (f << 13); 104 return (tag); 105 } 106 107 void 108 dwlpx_decompose_tag(cpv, tag, bp, dp, fp) 109 void *cpv; 110 pcitag_t tag; 111 int *bp, *dp, *fp; 112 { 113 114 if (bp != NULL) 115 *bp = (tag >> 24) & 0xff; 116 if (dp != NULL) { 117 int j, i = (tag >> 18) & 0xf; 118 j = -1; 119 while (i != 0) { 120 j++; 121 i >>= 1; 122 } 123 j += (((tag >> 22) & 3) << 2); 124 *dp = j; 125 } 126 if (fp != NULL) 127 *fp = (tag >> 13) & 0x7; 128 } 129 130 pcireg_t 131 dwlpx_conf_read(cpv, tag, offset) 132 void *cpv; 133 pcitag_t tag; 134 int offset; 135 { 136 struct dwlpx_config *ccp = cpv; 137 struct dwlpx_softc *sc; 138 pcireg_t *dp, data = (pcireg_t) -1; 139 unsigned long paddr; 140 int secondary, i, s = 0; 141 u_int32_t rvp; 142 143 if (ccp == NULL) { 144 panic("NULL ccp in dwlpx_conf_read\n"); 145 } 146 sc = ccp->cc_sc; 147 secondary = tag >> 24; 148 if (secondary) { 149 tag &= 0x1fffff; 150 tag |= (secondary << 21); 151 152 #if 0 153 printf("read secondary %d reg %x (tag %x)", 154 secondary, offset, tag); 155 #endif 156 157 alpha_pal_draina(); 158 s = splhigh(); 159 /* 160 * Set up HPCs for type 1 cycles. 161 */ 162 for (i = 0; i < sc->dwlpx_nhpc; i++) { 163 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 164 PCIA_CTL_T1CYC; 165 alpha_mb(); 166 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 167 alpha_mb(); 168 } 169 } 170 paddr = (unsigned long) tag; 171 paddr |= DWLPX_PCI_CONF; 172 paddr |= ((unsigned long) ((offset >> 2) << 7)); 173 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 174 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 175 paddr |= (1LL << 39); 176 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */ 177 178 dp = (pcireg_t *)KV(paddr); 179 if (badaddr(dp, sizeof (*dp)) == 0) { 180 data = *dp; 181 } 182 if (secondary) { 183 alpha_pal_draina(); 184 for (i = 0; i < sc->dwlpx_nhpc; i++) { 185 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & 186 ~PCIA_CTL_T1CYC; 187 alpha_mb(); 188 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 189 alpha_mb(); 190 } 191 (void) splx(s); 192 #if 0 193 printf("=%x\n", data); 194 #endif 195 } 196 return (data); 197 } 198 199 void 200 dwlpx_conf_write(cpv, tag, offset, data) 201 void *cpv; 202 pcitag_t tag; 203 int offset; 204 pcireg_t data; 205 { 206 struct dwlpx_config *ccp = cpv; 207 struct dwlpx_softc *sc; 208 pcireg_t *dp; 209 unsigned long paddr; 210 int secondary, i, s = 0; 211 u_int32_t rvp; 212 213 if (ccp == NULL) { 214 panic("NULL ccp in dwlpx_conf_write\n"); 215 } 216 sc = ccp->cc_sc; 217 secondary = tag >> 24; 218 if (secondary) { 219 tag &= 0x1fffff; 220 tag |= (secondary << 21); 221 #if 0 222 printf("write secondary %d reg %x (tag %x) with %x\n", 223 secondary, offset, tag, data); 224 #endif 225 226 alpha_pal_draina(); 227 s = splhigh(); 228 /* 229 * Set up HPCs for type 1 cycles. 230 */ 231 for (i = 0; i < sc->dwlpx_nhpc; i++) { 232 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) | 233 PCIA_CTL_T1CYC; 234 alpha_mb(); 235 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 236 alpha_mb(); 237 } 238 } 239 paddr = (unsigned long) tag; 240 paddr |= DWLPX_PCI_CONF; 241 paddr |= ((unsigned long) ((offset >> 2) << 7)); 242 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34); 243 paddr |= (((u_long) sc->dwlpx_node - 4) << 36); 244 paddr |= (1LL << 39); 245 paddr |= (3LL << 3); /* 32 bit PCI byte enables */ 246 247 dp = (pcireg_t *)KV(paddr); 248 *dp = data; 249 alpha_mb(); 250 if (secondary) { 251 alpha_pal_draina(); 252 for (i = 0; i < sc->dwlpx_nhpc; i++) { 253 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) & 254 ~PCIA_CTL_T1CYC; 255 alpha_mb(); 256 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp; 257 alpha_mb(); 258 } 259 (void) splx(s); 260 } 261 } 262
Indexes created Fri Sep 26 08:10:20 GMT 2025