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lcareg.h revision 1.9.64.1 
      1 /* $NetBSD: lcareg.h,v 1.9.64.1 2021/08/01 22:42:02 thorpej Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1995 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Authors: Jeffrey Hsu, Jason R. Thorpe
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 /*
     31  * 21066 chip registers
     32  */
     33 
     34 #define REGVAL(r)	(*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
     35 #define REGVAL64(r)	(*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r))
     36 
     37 /*
     38  * Base addresses
     39  */
     40 #define	LCA_MEMC_BASE	0x120000000L		/* LCA memory controller regs */
     41 #define LCA_IOC_BASE	0x180000000L		/* LCA IOC Regs */
     42 #define LCA_PCI_SIO	0x1c0000000L		/* PCI Sp. I/O Space */
     43 #define LCA_PCI_CONF	0x1e0000000L		/* PCI Conf. Space */
     44 #define LCA_PCI_SPARSE	0x200000000L		/* PCI Sparse Space */
     45 #define LCA_PCI_DENSE	0x300000000L		/* PCI Dense Space */
     46 
     47 #define LCA_MEMC_BCR0	(LCA_MEMC_BASE + 0x00)	/* Bank Configuration 0 */
     48 #define LCA_MEMC_BCR1	(LCA_MEMC_BASE + 0x08)	/* Bank Configuration 1 */
     49 #define LCA_MEMC_BCR2	(LCA_MEMC_BASE + 0x10)	/* Bank Configuration 2 */
     50 #define LCA_MEMC_BCR3	(LCA_MEMC_BASE + 0x18)	/* Bank Configuration 3 */
     51 #define LCA_MEMC_BMR0	(LCA_MEMC_BASE + 0x20)	/* Bank Address Mask 0 */
     52 #define LCA_MEMC_BMR1	(LCA_MEMC_BASE + 0x28)	/* Bank Address Mask 1 */
     53 #define LCA_MEMC_BMR2	(LCA_MEMC_BASE + 0x30)	/* Bank Address Mask 2 */
     54 #define LCA_MEMC_BMR3	(LCA_MEMC_BASE + 0x38)	/* Bank Address Mask 3 */
     55 #define LCA_MEMC_BTR0	(LCA_MEMC_BASE + 0x40)	/* Bank Timing 0 */
     56 #define LCA_MEMC_BTR1	(LCA_MEMC_BASE + 0x48)	/* Bank Timing 1 */
     57 #define LCA_MEMC_BTR2	(LCA_MEMC_BASE + 0x50)	/* Bank Timing 2 */
     58 #define LCA_MEMC_BTR3	(LCA_MEMC_BASE + 0x58)	/* Bank Timing 3 */
     59 #define LCA_MEMC_GTR	(LCA_MEMC_BASE + 0x60)	/* Global Timing */
     60 #define LCA_MEMC_ESR	(LCA_MEMC_BASE + 0x68)	/* Error Status */
     61 #define LCA_MEMC_EAR	(LCA_MEMC_BASE + 0x70)	/* Error Address */
     62 #define LCA_MEMC_CAR	(LCA_MEMC_BASE + 0x78)	/* Cache */
     63 #define LCA_MEMC_VGR	(LCA_MEMC_BASE + 0x80)	/* Video and Graphics Control */
     64 #define LCA_MEMC_PLM	(LCA_MEMC_BASE + 0x88)	/* Plane mask */
     65 #define LCA_MEMC_FOR	(LCA_MEMC_BASE + 0x90)	/* Foreground */
     66 
     67 #define MEMC_CAR_BCE	__BIT(0)	/* Bcache enable */
     68 #define MEMC_CAR_ETP	__BIT(2)	/* Enable tag parity check */
     69 #define MEMC_CAR_WWP	__BIT(3)	/* Write wrong tag parity */
     70 #define MEMC_CAR_ECE	__BIT(4)	/* Enable Bcache ECC */
     71 #define MEMC_CAR_BCS	__BITS(5,7)	/* Bcache size */
     72 #define MEMC_CAR_RCC	__BITS(8,10)	/* Read Cycle Count */
     73 #define MEMC_CAR_WCC	__BITS(11,13)	/* Write Cycle Count */
     74 #define MEMC_CAR_WHD	__BIT(14)	/* Write Hold Time */
     75 #define MEMC_CAR_PWR	__BIT(15)	/* Power Saving */
     76 #define MEMC_CAR_TAG	__BITS(16,30)	/* latched Bcache tag value */
     77 #define MEMC_CAR_HIT	__BIT(31)	/* Bcache hit */
     78 
     79 #define BCS_64K		0
     80 #define BCS_128K	1
     81 #define BCS_256K	2
     82 #define BCS_512K	3
     83 #define BCS_1M		4
     84 #define BCS_2M		5
     85 
     86 #define LCA_IOC_HAE	LCA_IOC_BASE		/* Host Address Ext. (64) */
     87 #define	IOC_HAE_ADDREXT	0x00000000f8000000UL
     88 #define	IOC_HAE_RSVSD	0xffffffff07ffffffUL
     89 
     90 #define LCA_IOC_CONF	(LCA_IOC_BASE + 0x020)	/* Configuration Cycle Type */
     91 
     92 #define LCA_IOC_STAT0	(LCA_IOC_BASE + 0x040)	/* Status 0 */
     93 #define	IOC_STAT0_CMD	0x000000000000000fUL	/* PCI command mask */
     94 #define	IOC_STAT0_ERR	0x0000000000000010UL	/* IOC error indicator R/W1C */
     95 #define	IOC_STAT0_LOST	0x0000000000000020UL	/* IOC lose error info R/W1C */
     96 #define	IOC_STAT0_THIT	0x0000000000000040UL	/* test hit */
     97 #define	IOC_STAT0_TREF	0x0000000000000080UL	/* test reference */
     98 #define	IOC_STAT0_CODE	0x0000000000000700UL	/* code mask */
     99 #define	IOC_STAT0_CODESHIFT 8
    100 #define	IOC_STAT0_P_NBR	0x00000000ffffe000UL	/* page number mask */
    101 
    102 #define LCA_IOC_STAT1	(LCA_IOC_BASE + 0x060)	/* Status 1 */
    103 #define	IOC_STAT1_ADDR	0x00000000ffffffffUL	/* PCI address mask */
    104 
    105 #define	LCA_IOC_TBIA	(LCA_IOC_BASE + 0x080)	/* TLB Invalidate All */
    106 #define	LCA_IOC_TB_ENA	(LCA_IOC_BASE + 0x0a0)	/* TLB Enable */
    107 #define	IOC_TB_ENA_TEN	0x0000000000000080UL
    108 
    109 #define LCA_IOC_W_BASE0	(LCA_IOC_BASE + 0x100)	/* Window Base */
    110 #define LCA_IOC_W_MASK0	(LCA_IOC_BASE + 0x140)	/* Window Mask */
    111 #define LCA_IOC_W_T_BASE0 (LCA_IOC_BASE + 0x180) /* Translated Base */
    112 
    113 #define LCA_IOC_W_BASE1	(LCA_IOC_BASE + 0x120)	/* Window Base */
    114 #define LCA_IOC_W_MASK1	(LCA_IOC_BASE + 0x160)	/* Window Mask */
    115 #define LCA_IOC_W_T_BASE1 (LCA_IOC_BASE + 0x1a0) /* Translated Base */
    116 
    117 #define	IOC_W_BASE_W_BASE 0x00000000fff00000UL	/* Window base value */
    118 #define	IOC_W_BASE_SG	  0x0000000100000000UL	/* Window uses SGMAPs */
    119 #define	IOC_W_BASE_WEN	  0x0000000200000000UL	/* Window enable */
    120 
    121 #define	IOC_W_MASK_1M	0x0000000000000000UL	/* 1MB window */
    122 #define	IOC_W_MASK_2M	0x0000000000100000UL	/* 2MB window */
    123 #define	IOC_W_MASK_4M	0x0000000000300000UL	/* 4MB window */
    124 #define	IOC_W_MASK_8M	0x0000000000700000UL	/* 8MB window */
    125 #define	IOC_W_MASK_16M	0x0000000000f00000UL	/* 16MB window */
    126 #define	IOC_W_MASK_32M	0x0000000001f00000UL	/* 32MB window */
    127 #define	IOC_W_MASK_64M	0x0000000003f00000UL	/* 64MB window */
    128 #define	IOC_W_MASK_128M	0x0000000007f00000UL	/* 128M window */
    129 #define	IOC_W_MASK_256M	0x000000000ff00000UL	/* 256M window */
    130 #define	IOC_W_MASK_512M	0x000000001ff00000UL	/* 512M window */
    131 #define	IOC_W_MASK_1G	0x000000003ff00000UL	/* 1GB window */
    132 #define	IOC_W_MASK_2G	0x000000007ff00000UL	/* 2GB window */
    133 #define	IOC_W_MASK_4G	0x00000000fff00000UL	/* 4GB window */
    134 
    135 #define	IOC_W_T_BASE	0x00000000fffffc00UL	/* page table base */
    136