mcpcia.c revision 1.10
1 /* $NetBSD: mcpcia.c,v 1.10 2000/06/25 19:32:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1998 by Matthew Jacob 42 * NASA AMES Research Center. 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice immediately at the beginning of the file, without modification, 50 * this list of conditions, and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 61 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 67 * SUCH DAMAGE. 68 */ 69 70 /* 71 * MCPCIA mcbus to PCI bus adapter 72 * found on AlphaServer 4100 systems. 73 */ 74 75 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 76 77 __KERNEL_RCSID(0, "$NetBSD: mcpcia.c,v 1.10 2000/06/25 19:32:19 thorpej Exp $"); 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 84 #include <machine/autoconf.h> 85 #include <machine/rpb.h> 86 #include <machine/pte.h> 87 #include <machine/sysarch.h> 88 89 #include <alpha/mcbus/mcbusreg.h> 90 #include <alpha/mcbus/mcbusvar.h> 91 #include <alpha/pci/mcpciareg.h> 92 #include <alpha/pci/mcpciavar.h> 93 #include <alpha/pci/pci_kn300.h> 94 95 #define KV(_addr) ((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr))) 96 #define MCPCIA_SYSBASE(mc) \ 97 ((((unsigned long) (mc)->cc_gid) << MCBUS_GID_SHIFT) | \ 98 (((unsigned long) (mc)->cc_mid) << MCBUS_MID_SHIFT) | \ 99 (MCBUS_IOSPACE)) 100 101 #define MCPCIA_PROBE(mid, gid) \ 102 badaddr((void *)KV(((((unsigned long) gid) << MCBUS_GID_SHIFT) | \ 103 (((unsigned long) mid) << MCBUS_MID_SHIFT) | \ 104 (MCBUS_IOSPACE) | MCPCIA_PCI_BRIDGE | _MCPCIA_PCI_REV)), \ 105 sizeof(u_int32_t)) 106 107 static int mcpciamatch __P((struct device *, struct cfdata *, void *)); 108 static void mcpciaattach __P((struct device *, struct device *, void *)); 109 struct cfattach mcpcia_ca = { 110 sizeof(struct mcpcia_softc), mcpciamatch, mcpciaattach 111 }; 112 113 static int mcpciaprint __P((void *, const char *)); 114 115 void mcpcia_init0 __P((struct mcpcia_config *, int)); 116 117 /* 118 * We have one statically-allocated mcpcia_config structure; this is 119 * the one used for the console (which, coincidentally, is the only 120 * MCPCIA with an EISA adapter attached to it). 121 */ 122 struct mcpcia_config mcpcia_console_configuration; 123 124 int mcpcia_bus_get_window __P((int, int, 125 struct alpha_bus_space_translation *abst)); 126 127 static int 128 mcpciaprint(aux, pnp) 129 void *aux; 130 const char *pnp; 131 { 132 register struct pcibus_attach_args *pba = aux; 133 /* only PCIs can attach to MCPCIA for now */ 134 if (pnp) 135 printf("%s at %s", pba->pba_busname, pnp); 136 printf(" bus %d", pba->pba_bus); 137 return (UNCONF); 138 } 139 140 static int 141 mcpciamatch(parent, cf, aux) 142 struct device *parent; 143 struct cfdata *cf; 144 void *aux; 145 { 146 struct mcbus_dev_attach_args *ma = aux; 147 if (ma->ma_type == MCBUS_TYPE_PCI) 148 return (1); 149 return (0); 150 } 151 152 static void 153 mcpciaattach(parent, self, aux) 154 struct device *parent; 155 struct device *self; 156 void *aux; 157 { 158 static int first = 1; 159 struct mcbus_dev_attach_args *ma = aux; 160 struct mcpcia_softc *mcp = (struct mcpcia_softc *)self; 161 struct mcpcia_config *ccp; 162 struct pcibus_attach_args pba; 163 u_int32_t ctl; 164 165 /* 166 * Make sure this MCPCIA exists... 167 */ 168 if (MCPCIA_PROBE(ma->ma_mid, ma->ma_gid)) { 169 mcp->mcpcia_cc = NULL; 170 printf(" (not present)\n"); 171 return; 172 } 173 printf("\n"); 174 175 /* 176 * Determine if we're the console's MCPCIA. 177 */ 178 if (ma->ma_mid == mcpcia_console_configuration.cc_mid && 179 ma->ma_gid == mcpcia_console_configuration.cc_gid) 180 ccp = &mcpcia_console_configuration; 181 else { 182 ccp = malloc(sizeof(struct mcpcia_config), M_DEVBUF, M_WAITOK); 183 memset(ccp, 0, sizeof(struct mcpcia_config)); 184 185 ccp->cc_mid = ma->ma_mid; 186 ccp->cc_gid = ma->ma_gid; 187 } 188 189 mcp->mcpcia_cc = ccp; 190 ccp->cc_sc = mcp; 191 192 /* This initializes cc_sysbase so we can do register access. */ 193 mcpcia_init0(ccp, 1); 194 195 ctl = REGVAL(MCPCIA_PCI_REV(ccp)); 196 printf("%s: Horse Revision %d, %s Handed Saddle Revision %d," 197 " CAP Revision %d\n", mcp->mcpcia_dev.dv_xname, HORSE_REV(ctl), 198 (SADDLE_TYPE(ctl) & 1)? "Right": "Left", SADDLE_REV(ctl), 199 CAP_REV(ctl)); 200 201 mcpcia_dma_init(ccp); 202 203 /* 204 * Set up interrupts 205 */ 206 pci_kn300_pickintr(ccp, first); 207 first = 0; 208 209 /* 210 * Attach PCI bus 211 */ 212 pba.pba_busname = "pci"; 213 pba.pba_iot = &ccp->cc_iot; 214 pba.pba_memt = &ccp->cc_memt; 215 pba.pba_dmat = /* start with direct, may change... */ 216 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI); 217 pba.pba_pc = &ccp->cc_pc; 218 pba.pba_bus = 0; 219 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 220 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 221 (void) config_found(self, &pba, mcpciaprint); 222 223 /* 224 * Clear any errors that may have occurred during the probe 225 * sequence. 226 */ 227 REGVAL(MCPCIA_CAP_ERR(ccp)) = 0xFFFFFFFF; 228 alpha_mb(); 229 } 230 231 void 232 mcpcia_init() 233 { 234 struct mcpcia_config *ccp = &mcpcia_console_configuration; 235 int i; 236 237 /* 238 * Look for all of the MCPCIAs on the system. One of them 239 * will have an EISA attached to it. This MCPCIA is the 240 * only one that can be used for the console. Once we find 241 * that one, initialize it. 242 */ 243 244 for (i = 0; i < MCPCIA_PER_MCBUS; i++) { 245 ccp->cc_mid = mcbus_mcpcia_probe_order[i]; 246 /* 247 * XXX If we ever support more than one MCBUS, we'll 248 * XXX have to probe for them, and map them to unit 249 * XXX numbers. 250 */ 251 ccp->cc_gid = MCBUS_GID_FROM_INSTANCE(0); 252 ccp->cc_sysbase = MCPCIA_SYSBASE(ccp); 253 254 if (badaddr((void *)ALPHA_PHYS_TO_K0SEG(MCPCIA_PCI_REV(ccp)), 255 sizeof(u_int32_t))) 256 continue; 257 258 if (EISA_PRESENT(REGVAL(MCPCIA_PCI_REV(ccp)))) { 259 mcpcia_init0(ccp, 0); 260 261 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 2; 262 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 3; 263 264 alpha_bus_get_window = mcpcia_bus_get_window; 265 return; 266 } 267 } 268 269 panic("mcpcia_init: unable to find EISA bus"); 270 } 271 272 void 273 mcpcia_init0(ccp, mallocsafe) 274 struct mcpcia_config *ccp; 275 int mallocsafe; 276 { 277 u_int32_t ctl; 278 279 if (ccp->cc_initted == 0) { 280 /* don't do these twice since they set up extents */ 281 mcpcia_bus_io_init(&ccp->cc_iot, ccp); 282 mcpcia_bus_mem_init(&ccp->cc_memt, ccp); 283 } 284 ccp->cc_mallocsafe = mallocsafe; 285 286 mcpcia_pci_init(&ccp->cc_pc, ccp); 287 288 /* 289 * Establish a precalculated base for convenience's sake. 290 */ 291 ccp->cc_sysbase = MCPCIA_SYSBASE(ccp); 292 293 /* 294 * Disable interrupts and clear errors prior to probing 295 */ 296 REGVAL(MCPCIA_INT_MASK0(ccp)) = 0; 297 REGVAL(MCPCIA_INT_MASK1(ccp)) = 0; 298 REGVAL(MCPCIA_CAP_ERR(ccp)) = 0xFFFFFFFF; 299 alpha_mb(); 300 301 /* 302 * Use this opportunity to also find out the MID and CPU 303 * type of the currently running CPU (that's us, billybob....) 304 */ 305 ctl = REGVAL(MCPCIA_WHOAMI(ccp)); 306 mcbus_primary.mcbus_cpu_mid = MCBUS_CPU_MID(ctl); 307 if ((MCBUS_CPU_INFO(ctl) & CPU_Fill_Err) == 0 && 308 mcbus_primary.mcbus_valid == 0) { 309 mcbus_primary.mcbus_bcache = 310 MCBUS_CPU_INFO(ctl) & CPU_BCacheMask; 311 mcbus_primary.mcbus_valid = 1; 312 } 313 alpha_mb(); 314 315 ccp->cc_initted = 1; 316 } 317 318 #ifdef TEST_PROBE_DEATH 319 static void 320 die_heathen_dog(arg) 321 void *arg; 322 { 323 struct mcpcia_config *ccp = arg; 324 325 /* this causes a fatal machine check (0x670) */ 326 REGVAL(MCPCIA_CAP_DIAG(ccp)) |= CAP_DIAG_MC_ADRPE; 327 } 328 #endif 329 330 void 331 mcpcia_config_cleanup() 332 { 333 volatile u_int32_t ctl; 334 struct mcpcia_softc *mcp; 335 struct mcpcia_config *ccp; 336 int i; 337 extern struct cfdriver mcpcia_cd; 338 339 /* 340 * Turn on Hard, Soft error interrupts. Maybe i2c too. 341 */ 342 for (i = 0; i < mcpcia_cd.cd_ndevs; i++) { 343 if ((mcp = mcpcia_cd.cd_devs[i]) == NULL) 344 continue; 345 346 ccp = mcp->mcpcia_cc; 347 if (ccp == NULL) 348 continue; 349 350 ctl = REGVAL(MCPCIA_INT_MASK0(ccp)); 351 ctl |= MCPCIA_GEN_IENABL; 352 REGVAL(MCPCIA_INT_MASK0(ccp)) = ctl; 353 alpha_mb(); 354 355 /* force stall while write completes */ 356 ctl = REGVAL(MCPCIA_INT_MASK0(ccp)); 357 } 358 #ifdef TEST_PROBE_DEATH 359 (void) timeout (die_heathen_dog, &mcpcia_console_configuration, 360 30 * hz); 361 #endif 362 } 363 364 int 365 mcpcia_bus_get_window(type, window, abst) 366 int type, window; 367 struct alpha_bus_space_translation *abst; 368 { 369 struct mcpcia_config *ccp = &mcpcia_console_configuration; 370 bus_space_tag_t st; 371 372 switch (type) { 373 case ALPHA_BUS_TYPE_PCI_IO: 374 st = &ccp->cc_iot; 375 break; 376 377 case ALPHA_BUS_TYPE_PCI_MEM: 378 st = &ccp->cc_memt; 379 break; 380 381 default: 382 panic("mcpcia_bus_get_window"); 383 } 384 385 return (alpha_bus_space_get_window(st, window, abst)); 386 } 387
Indexes created Mon Sep 29 03:10:08 GMT 2025