pci_1000a.c revision 1.1
1 /* $NetBSD: pci_1000a.c,v 1.1 1998/06/24 01:41:16 ross Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at 8 * Carnegie-Mellon University. Platform support for Noritake, Pintake, and 9 * Corelle by Ross Harvey with copyright assignment by permission of Avalon 10 * Computer Systems, Inc. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 43 * All rights reserved. 44 * 45 * Author: Chris G. Demetriou 46 * 47 * Permission to use, copy, modify and distribute this software and 48 * its documentation is hereby granted, provided that both the copyright 49 * notice and this permission notice appear in all copies of the 50 * software, derivative works or modified versions, and any portions 51 * thereof, and that both notices appear in supporting documentation. 52 * 53 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 54 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 55 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 56 * 57 * Carnegie Mellon requests users of this software to return to 58 * 59 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 60 * School of Computer Science 61 * Carnegie Mellon University 62 * Pittsburgh PA 15213-3890 63 * 64 * any improvements or extensions that they make and grant Carnegie the 65 * rights to redistribute these changes. 66 */ 67 68 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 69 70 __KERNEL_RCSID(0, "$NetBSD: pci_1000a.c,v 1.1 1998/06/24 01:41:16 ross Exp $"); 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/time.h> 75 #include <sys/systm.h> 76 #include <sys/errno.h> 77 #include <sys/malloc.h> 78 #include <sys/device.h> 79 #include <sys/syslog.h> 80 81 #include <vm/vm.h> 82 83 #include <machine/autoconf.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 88 #include <alpha/pci/pci_1000a.h> 89 90 #ifndef EVCNT_COUNTERS 91 #include <machine/intrcnt.h> 92 #endif 93 94 #include "sio.h" 95 #if NSIO 96 #include <alpha/pci/siovar.h> 97 #endif 98 99 #define IMR2IRQ(bn) ((bn) - 1) 100 #define IRQ2IMR(irq) ((irq) + 1) 101 102 static bus_space_tag_t mystery_icu_iot; 103 static bus_space_handle_t mystery_icu_ioh[2]; 104 105 int dec_1000a_intr_map __P((void *, pcitag_t, int, int, 106 pci_intr_handle_t *)); 107 const char *dec_1000a_intr_string __P((void *, pci_intr_handle_t)); 108 void *dec_1000a_intr_establish __P((void *, pci_intr_handle_t, 109 int, int (*func)(void *), void *)); 110 void dec_1000a_intr_disestablish __P((void *, void *)); 111 112 #define DEC_1000A_MAX_IRQ 32 113 #define PCI_STRAY_MAX 5 114 115 struct alpha_shared_intr *dec_1000a_pci_intr; 116 #ifdef EVCNT_COUNTERS 117 struct evcnt dec_1000a_intr_evcnt; 118 #endif 119 120 static void dec_1000a_iointr __P((void *framep, unsigned long vec)); 121 static void dec_1000a_enable_intr __P((int irq)); 122 static void dec_1000a_disable_intr __P((int irq)); 123 static void pci_1000a_imi __P((void)); 124 static pci_chipset_tag_t pc_tag; 125 126 int ross_tmp_didr; /* XXX XXX XXX */ 127 int ross_tmp_didv; /* XXX XXX XXX */ 128 129 void 130 pci_1000a_pickintr(core, iot, memt, pc) 131 void *core; 132 bus_space_tag_t iot, memt; 133 pci_chipset_tag_t pc; 134 { 135 int i; 136 mystery_icu_iot = iot; 137 138 pc_tag = pc; 139 if (bus_space_map(iot, 0x54a, 2, 0, mystery_icu_ioh + 0) 140 || bus_space_map(iot, 0x54c, 2, 0, mystery_icu_ioh + 1)) 141 panic("pci_1000a_pickintr"); 142 pc->pc_intr_v = core; 143 pc->pc_intr_map = dec_1000a_intr_map; 144 pc->pc_intr_string = dec_1000a_intr_string; 145 pc->pc_intr_establish = dec_1000a_intr_establish; 146 pc->pc_intr_disestablish = dec_1000a_intr_disestablish; 147 148 pc->pc_pciide_compat_intr_establish = NULL; 149 150 dec_1000a_pci_intr = alpha_shared_intr_alloc(DEC_1000A_MAX_IRQ); 151 for (i = 0; i < DEC_1000A_MAX_IRQ; i++) 152 alpha_shared_intr_set_maxstrays(dec_1000a_pci_intr, i, 153 PCI_STRAY_MAX); 154 155 pci_1000a_imi(); 156 #if NSIO 157 sio_intr_setup(pc, iot); 158 #endif 159 set_iointr(dec_1000a_iointr); 160 } 161 162 int 163 dec_1000a_intr_map(ccv, bustag, buspin, line, ihp) 164 void *ccv; 165 pcitag_t bustag; 166 int buspin, line; 167 pci_intr_handle_t *ihp; 168 { 169 int imrbit, device; 170 /* 171 * Get bit number in mystery ICU imr 172 */ 173 static const signed char imrmap[][4] = { 174 # define IRQSPLIT(o) { (o), (o)+1, (o)+16, (o)+16+1 } 175 # define IRQNONE { 0, 0, 0, 0 } 176 /* 0 */ { 1, 0, 0, 0 }, /* Noritake and Pintake */ 177 /* 1 */ IRQSPLIT(8), 178 /* 2 */ IRQSPLIT(10), 179 /* 3 */ IRQSPLIT(12), 180 /* 4 */ IRQSPLIT(14), 181 /* 5 */ { 1, 0, 0, 0 }, /* Corelle */ 182 /* 6 */ { 10, 0, 0, 0 }, /* Corelle */ 183 /* 7 */ IRQNONE, 184 /* 8 */ IRQNONE, 185 /* 9 */ IRQNONE, 186 /* 10 */ IRQNONE, 187 /* 11 */ IRQSPLIT(2), 188 /* 12 */ IRQSPLIT(4), 189 /* 13 */ IRQSPLIT(6), 190 /* 14 */ IRQSPLIT(8) /* Corelle */ 191 }; 192 193 if (buspin == 0) /* No IRQ used. */ 194 return 1; 195 if (!(1 <= buspin && buspin <= 4)) 196 goto bad; 197 alpha_pci_decompose_tag(pc_tag, bustag, NULL, &device, NULL); 198 if (0 <= device && device < sizeof imrmap / sizeof imrmap[0]) { 199 imrbit = imrmap[device][buspin - 1]; 200 if (imrbit) { 201 *ihp = IMR2IRQ(imrbit); 202 return 0; 203 } 204 } 205 bad: printf("dec_1000a_intr_map: can't map dev %d pin %d\n", device, buspin); 206 return 1; 207 } 208 209 const char * 210 dec_1000a_intr_string(ccv, ih) 211 void *ccv; 212 pci_intr_handle_t ih; 213 { 214 static const char irqmsg_fmt[] = "dec_1000a irq %ld"; 215 static char irqstr[sizeof irqmsg_fmt]; 216 217 218 if (ih > DEC_1000A_MAX_IRQ) 219 panic("dec_1000a_intr_string: bogus dec_1000a IRQ 0x%x\n", ih); 220 221 sprintf(irqstr, irqmsg_fmt, ih); 222 return (irqstr); 223 } 224 225 void * 226 dec_1000a_intr_establish(ccv, ih, level, func, arg) 227 void *ccv, *arg; 228 pci_intr_handle_t ih; 229 int level; 230 int (*func) __P((void *)); 231 { 232 void *cookie; 233 234 if (ih > DEC_1000A_MAX_IRQ) 235 panic("dec_1000a_intr_establish: IRQ too high, 0x%x\n", ih); 236 237 cookie = alpha_shared_intr_establish(dec_1000a_pci_intr, ih, IST_LEVEL, 238 level, func, arg, "dec_1000a irq"); 239 240 if (cookie != NULL && 241 alpha_shared_intr_isactive(dec_1000a_pci_intr, ih)) 242 dec_1000a_enable_intr(ih); 243 return (cookie); 244 } 245 246 void 247 dec_1000a_intr_disestablish(ccv, cookie) 248 void *ccv, *cookie; 249 { 250 panic("dec_1000a_intr_disestablish not implemented"); /* XXX */ 251 } 252 253 static void 254 dec_1000a_iointr(framep, vec) 255 void *framep; 256 unsigned long vec; 257 { 258 int irq; 259 260 if (ross_tmp_didv) 261 printf("\tvec 0x%x\n", vec); 262 if (vec >= 0x900) { 263 if (vec >= 0x900 + (DEC_1000A_MAX_IRQ << 4)) 264 panic("dec_1000a_iointr: vec 0x%x out of range\n", vec); 265 irq = (vec - 0x900) >> 4; 266 #ifdef EVCNT_COUNTERS 267 dec_1000a_intr_evcnt.ev_count++; 268 #else 269 if (DEC_1000A_MAX_IRQ != INTRCNT_DEC_1000A_IRQ_LEN) 270 panic("dec_1000a interrupt counter sizes inconsistent"); 271 intrcnt[INTRCNT_DEC_1000A_IRQ + irq]++; 272 #endif 273 274 if (!alpha_shared_intr_dispatch(dec_1000a_pci_intr, irq)) { 275 alpha_shared_intr_stray(dec_1000a_pci_intr, irq, 276 "dec_1000a irq"); 277 if (dec_1000a_pci_intr[irq].intr_nstrays == 278 dec_1000a_pci_intr[irq].intr_maxstrays) 279 dec_1000a_disable_intr(irq); 280 } 281 return; 282 } 283 #if NSIO 284 if (vec >= 0x800) { 285 sio_iointr(framep, vec); 286 return; 287 } 288 #endif 289 panic("dec_1000a_iointr: weird vec 0x%x\n", vec); 290 } 291 292 /* 293 * Read and write the mystery ICU IMR registers 294 */ 295 296 #define IR(h) bus_space_read_2(mystery_icu_iot, mystery_icu_ioh[h], 0) 297 #define IW(h, v) bus_space_write_2(mystery_icu_iot, mystery_icu_ioh[h], 0, (v)) 298 299 /* 300 * Enable and disable interrupts at the ICU level 301 */ 302 303 static void 304 dec_1000a_enable_intr(irq) 305 int irq; 306 { 307 int imrval = IRQ2IMR(irq); 308 int i = imrval >= 16; 309 310 if (ross_tmp_didr) { 311 IW(0, ~0); 312 IW(1, ~0); 313 return; 314 } 315 IW(i, IR(i) | 1 << (imrval & 0xf)); 316 } 317 318 static void 319 dec_1000a_disable_intr(irq) 320 int irq; 321 { 322 int imrval = IRQ2IMR(irq); 323 int i = imrval >= 16; 324 325 IW(i, IR(i) & ~(1 << (imrval & 0xf))); 326 } 327 /* 328 * Initialize mystery ICU 329 */ 330 static void 331 pci_1000a_imi() 332 { 333 IW(0, IR(0) & 1); 334 IW(1, IR(0) & 3); 335 } 336
Indexes created Tue Sep 30 20:09:53 GMT 2025