pci_2100_a50.c revision 1.1 1 1.1 cgd /* $NetBSD: pci_2100_a50.c,v 1.1 1995/06/28 01:25:43 cgd Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.1 cgd * Copyright (c) 1994, 1995 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Author: Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.1 cgd
30 1.1 cgd #include <sys/types.h>
31 1.1 cgd #include <sys/param.h>
32 1.1 cgd #include <sys/time.h>
33 1.1 cgd #include <sys/systm.h>
34 1.1 cgd #include <sys/errno.h>
35 1.1 cgd #include <sys/device.h>
36 1.1 cgd
37 1.1 cgd #include <vm/vm.h>
38 1.1 cgd
39 1.1 cgd #include <dev/isa/isavar.h>
40 1.1 cgd #include <alpha/isa/isa_intr.h>
41 1.1 cgd
42 1.1 cgd #include <dev/pci/pcivar.h>
43 1.1 cgd #include <dev/pci/pcireg.h>
44 1.1 cgd #include <alpha/pci/pci_chipset.h>
45 1.1 cgd
46 1.1 cgd void pci_2100_a50_attach __P((struct device *, struct device *, void *));
47 1.1 cgd void *pci_2100_a50_map_int __P((pcitag_t, pci_intrlevel, int (*) (void *),
48 1.1 cgd void *, int));
49 1.1 cgd
50 1.1 cgd struct pci_cfg_fcns pci_2100_a50_sio1_cfg_fcns = { /* XXX diff? */
51 1.1 cgd pci_2100_a50_attach, pci_2100_a50_map_int,
52 1.1 cgd };
53 1.1 cgd
54 1.1 cgd struct pci_cfg_fcns pci_2100_a50_sio2_cfg_fcns = {
55 1.1 cgd pci_2100_a50_attach, pci_2100_a50_map_int,
56 1.1 cgd };
57 1.1 cgd
58 1.1 cgd void
59 1.1 cgd pci_2100_a50_attach(parent, self, aux)
60 1.1 cgd struct device *parent, *self;
61 1.1 cgd void *aux;
62 1.1 cgd {
63 1.1 cgd int bus, device;
64 1.1 cgd
65 1.1 cgd #if 0
66 1.1 cgd for (bus = 0; bus <= 255; bus++)
67 1.1 cgd #else
68 1.1 cgd /*
69 1.1 cgd * XXX
70 1.1 cgd * Some current chipsets do wacky things with bus numbers > 0.
71 1.1 cgd * This seems like a violation of protocol, but the PCI BIOS does
72 1.1 cgd * allow one to query the maximum bus number, and eventually we
73 1.1 cgd * should do so.
74 1.1 cgd */
75 1.1 cgd for (bus = 0; bus <= 0; bus++)
76 1.1 cgd #endif
77 1.1 cgd for (device = 0; device <= 31; device++)
78 1.1 cgd pci_attach_subdev(self, bus, device);
79 1.1 cgd }
80 1.1 cgd
81 1.1 cgd void *
82 1.1 cgd pci_2100_a50_map_int(tag, level, func, arg, pin)
83 1.1 cgd pcitag_t tag;
84 1.1 cgd pci_intrlevel level;
85 1.1 cgd int (*func) __P((void *));
86 1.1 cgd void *arg;
87 1.1 cgd int pin;
88 1.1 cgd {
89 1.1 cgd int bus, device, pirq;
90 1.1 cgd pcireg_t pirqreg;
91 1.1 cgd u_int8_t line;
92 1.1 cgd
93 1.1 cgd bus = (tag >> 21) & 0xff; /* XXX */
94 1.1 cgd device = (tag >> 16) & 0x1f;
95 1.1 cgd
96 1.1 cgd if (bus != 0) /* XXX */
97 1.1 cgd return NULL;
98 1.1 cgd
99 1.1 cgd switch (device) {
100 1.1 cgd case 6: /* NCR SCSI */
101 1.1 cgd pirq = 3;
102 1.1 cgd break;
103 1.1 cgd
104 1.1 cgd case 11: /* slot 1 */
105 1.1 cgd switch (pin) {
106 1.1 cgd case PCI_INTERRUPT_PIN_A:
107 1.1 cgd case PCI_INTERRUPT_PIN_D:
108 1.1 cgd pirq = 0;
109 1.1 cgd break;
110 1.1 cgd case PCI_INTERRUPT_PIN_B:
111 1.1 cgd pirq = 2;
112 1.1 cgd break;
113 1.1 cgd case PCI_INTERRUPT_PIN_C:
114 1.1 cgd pirq = 1;
115 1.1 cgd break;
116 1.1 cgd };
117 1.1 cgd break;
118 1.1 cgd
119 1.1 cgd case 12: /* slot 2 */
120 1.1 cgd switch (pin) {
121 1.1 cgd case PCI_INTERRUPT_PIN_A:
122 1.1 cgd case PCI_INTERRUPT_PIN_D:
123 1.1 cgd pirq = 1;
124 1.1 cgd break;
125 1.1 cgd case PCI_INTERRUPT_PIN_B:
126 1.1 cgd pirq = 0;
127 1.1 cgd break;
128 1.1 cgd case PCI_INTERRUPT_PIN_C:
129 1.1 cgd pirq = 2;
130 1.1 cgd break;
131 1.1 cgd };
132 1.1 cgd break;
133 1.1 cgd
134 1.1 cgd case 13: /* slot 3 */
135 1.1 cgd switch (pin) {
136 1.1 cgd case PCI_INTERRUPT_PIN_A:
137 1.1 cgd case PCI_INTERRUPT_PIN_D:
138 1.1 cgd pirq = 2;
139 1.1 cgd break;
140 1.1 cgd case PCI_INTERRUPT_PIN_B:
141 1.1 cgd pirq = 1;
142 1.1 cgd break;
143 1.1 cgd case PCI_INTERRUPT_PIN_C:
144 1.1 cgd pirq = 0;
145 1.1 cgd break;
146 1.1 cgd };
147 1.1 cgd break;
148 1.1 cgd }
149 1.1 cgd
150 1.1 cgd pirqreg = pci_conf_read(pci_make_tag(0, 7, 0), 0x60); /* XXX */
151 1.1 cgd #if 0
152 1.1 cgd printf("pci_2100_a50_map_int: device %d pin %c: pirq %d, reg = %x\n",
153 1.1 cgd device, '@' + pin, pirq, pirqreg);
154 1.1 cgd #endif
155 1.1 cgd line = (pirqreg >> (pirq * 8)) & 0xff;
156 1.1 cgd if ((line & 0x80) != 0)
157 1.1 cgd return 0; /* not routed? */
158 1.1 cgd line &= 0xf;
159 1.1 cgd
160 1.1 cgd #if 0
161 1.1 cgd printf("pci_2100_a50_map_int: device %d pin %c: mapped to line %d\n",
162 1.1 cgd device, '@' + pin, line);
163 1.1 cgd #endif
164 1.1 cgd
165 1.1 cgd return isa_intr_establish(line, ISA_IST_LEVEL, pcilevel_to_isa(level),
166 1.1 cgd func, arg);
167 1.1 cgd }
168 1.1 cgd
169 1.1 cgd void
170 1.1 cgd pci_2100_a50_pickintr()
171 1.1 cgd {
172 1.1 cgd pcireg_t sioclass;
173 1.1 cgd int sioII;
174 1.1 cgd
175 1.1 cgd /* XXX MAGIC NUMBER */
176 1.1 cgd sioclass = pci_conf_read(pci_make_tag(0, 7, 0), PCI_CLASS_REG);
177 1.1 cgd sioII = (sioclass & 0xff) >= 3;
178 1.1 cgd if (!sioII)
179 1.1 cgd printf("WARNING: SIO NOT SIO II... NO BETS...\n");
180 1.1 cgd
181 1.1 cgd if (!sioII)
182 1.1 cgd pci_cfg_fcns = &pci_2100_a50_sio1_cfg_fcns;
183 1.1 cgd else
184 1.1 cgd pci_cfg_fcns = &pci_2100_a50_sio2_cfg_fcns;
185 1.1 cgd
186 1.1 cgd isa_intr_fcns = &sio_intr_fcns;
187 1.1 cgd (*isa_intr_fcns->isa_intr_setup)();
188 1.1 cgd set_iointr(isa_intr_fcns->isa_iointr);
189 1.1 cgd }
190