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pci_2100_a50.c revision 1.13
      1  1.13       cgd /* $NetBSD: pci_2100_a50.c,v 1.13 1997/04/07 02:01:20 cgd Exp $ */
      2   1.1       cgd 
      3   1.1       cgd /*
      4   1.6       cgd  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
      5   1.1       cgd  * All rights reserved.
      6   1.1       cgd  *
      7   1.1       cgd  * Author: Chris G. Demetriou
      8   1.1       cgd  *
      9   1.1       cgd  * Permission to use, copy, modify and distribute this software and
     10   1.1       cgd  * its documentation is hereby granted, provided that both the copyright
     11   1.1       cgd  * notice and this permission notice appear in all copies of the
     12   1.1       cgd  * software, derivative works or modified versions, and any portions
     13   1.1       cgd  * thereof, and that both notices appear in supporting documentation.
     14   1.1       cgd  *
     15   1.1       cgd  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16   1.1       cgd  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17   1.1       cgd  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18   1.1       cgd  *
     19   1.1       cgd  * Carnegie Mellon requests users of this software to return to
     20   1.1       cgd  *
     21   1.1       cgd  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22   1.1       cgd  *  School of Computer Science
     23   1.1       cgd  *  Carnegie Mellon University
     24   1.1       cgd  *  Pittsburgh PA 15213-3890
     25   1.1       cgd  *
     26   1.1       cgd  * any improvements or extensions that they make and grant Carnegie the
     27   1.1       cgd  * rights to redistribute these changes.
     28   1.1       cgd  */
     29  1.13       cgd 
     30  1.13       cgd #include <machine/options.h>		/* Pull in config options headers */
     31   1.1       cgd 
     32   1.1       cgd #include <sys/types.h>
     33   1.1       cgd #include <sys/param.h>
     34   1.1       cgd #include <sys/time.h>
     35   1.1       cgd #include <sys/systm.h>
     36   1.1       cgd #include <sys/errno.h>
     37   1.1       cgd #include <sys/device.h>
     38   1.1       cgd #include <vm/vm.h>
     39   1.1       cgd 
     40   1.8       cgd #include <machine/autoconf.h>
     41   1.5       cgd #include <machine/bus.h>
     42   1.5       cgd #include <machine/intr.h>
     43   1.5       cgd 
     44   1.1       cgd #include <dev/isa/isavar.h>
     45   1.3       cgd #include <dev/pci/pcireg.h>
     46   1.1       cgd #include <dev/pci/pcivar.h>
     47   1.1       cgd 
     48   1.3       cgd #include <alpha/pci/apecsvar.h>
     49   1.1       cgd 
     50   1.3       cgd #include <alpha/pci/pci_2100_a50.h>
     51   1.3       cgd #include <alpha/pci/siovar.h>
     52   1.7       cgd #include <alpha/pci/sioreg.h>
     53   1.1       cgd 
     54   1.3       cgd #include "sio.h"
     55   1.1       cgd 
     56   1.5       cgd int	dec_2100_a50_intr_map __P((void *, pcitag_t, int, int,
     57   1.5       cgd 	    pci_intr_handle_t *));
     58   1.5       cgd const char *dec_2100_a50_intr_string __P((void *, pci_intr_handle_t));
     59   1.5       cgd void    *dec_2100_a50_intr_establish __P((void *, pci_intr_handle_t,
     60   1.5       cgd 	    int, int (*func)(void *), void *));
     61   1.5       cgd void    dec_2100_a50_intr_disestablish __P((void *, void *));
     62   1.5       cgd 
     63   1.7       cgd #define	APECS_SIO_DEVICE	7	/* XXX */
     64   1.7       cgd 
     65   1.5       cgd void
     66   1.5       cgd pci_2100_a50_pickintr(acp)
     67   1.5       cgd 	struct apecs_config *acp;
     68   1.5       cgd {
     69  1.11       cgd 	bus_space_tag_t iot = acp->ac_iot;
     70   1.5       cgd 	pci_chipset_tag_t pc = &acp->ac_pc;
     71   1.5       cgd 	pcireg_t sioclass;
     72   1.5       cgd 	int sioII;
     73   1.5       cgd 
     74   1.5       cgd 	/* XXX MAGIC NUMBER */
     75   1.5       cgd 	sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG);
     76   1.5       cgd         sioII = (sioclass & 0xff) >= 3;
     77   1.5       cgd 
     78   1.5       cgd 	if (!sioII)
     79  1.10  christos 		printf("WARNING: SIO NOT SIO II... NO BETS...\n");
     80   1.5       cgd 
     81   1.5       cgd 	pc->pc_intr_v = acp;
     82   1.5       cgd 	pc->pc_intr_map = dec_2100_a50_intr_map;
     83   1.5       cgd 	pc->pc_intr_string = dec_2100_a50_intr_string;
     84   1.5       cgd 	pc->pc_intr_establish = dec_2100_a50_intr_establish;
     85   1.5       cgd 	pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish;
     86   1.1       cgd 
     87   1.5       cgd #if NSIO
     88  1.11       cgd         sio_intr_setup(iot);
     89   1.5       cgd 	set_iointr(&sio_iointr);
     90   1.5       cgd #else
     91   1.5       cgd 	panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)");
     92   1.5       cgd #endif
     93   1.5       cgd }
     94   1.5       cgd 
     95   1.5       cgd int
     96   1.5       cgd dec_2100_a50_intr_map(acv, bustag, buspin, line, ihp)
     97   1.3       cgd 	void *acv;
     98   1.5       cgd         pcitag_t bustag;
     99   1.5       cgd 	int buspin, line;
    100   1.5       cgd 	pci_intr_handle_t *ihp;
    101   1.1       cgd {
    102   1.3       cgd 	struct apecs_config *acp = acv;
    103   1.5       cgd 	pci_chipset_tag_t pc = &acp->ac_pc;
    104   1.5       cgd 	int device, pirq;
    105   1.5       cgd 	pcireg_t pirqreg;
    106   1.3       cgd 	u_int8_t pirqline;
    107   1.1       cgd 
    108   1.5       cgd         if (buspin == 0) {
    109   1.3       cgd                 /* No IRQ used. */
    110   1.5       cgd                 return 1;
    111   1.3       cgd         }
    112   1.5       cgd         if (buspin > 4) {
    113  1.12       cgd                 printf("dec_2100_a50_intr_map: bad interrupt pin %d\n",
    114  1.12       cgd 		    buspin);
    115   1.5       cgd                 return 1;
    116   1.3       cgd         }
    117   1.1       cgd 
    118   1.5       cgd 	pci_decompose_tag(pc, bustag, NULL, &device, NULL);
    119   1.1       cgd 
    120   1.1       cgd 	switch (device) {
    121   1.1       cgd 	case 6:					/* NCR SCSI */
    122   1.1       cgd 		pirq = 3;
    123   1.1       cgd 		break;
    124   1.1       cgd 
    125   1.1       cgd 	case 11:				/* slot 1 */
    126   1.5       cgd 	case 14:				/* slot 3 */
    127   1.5       cgd 		switch (buspin) {
    128   1.1       cgd 		case PCI_INTERRUPT_PIN_A:
    129   1.1       cgd 		case PCI_INTERRUPT_PIN_D:
    130   1.1       cgd 			pirq = 0;
    131   1.1       cgd 			break;
    132   1.1       cgd 		case PCI_INTERRUPT_PIN_B:
    133   1.1       cgd 			pirq = 2;
    134   1.1       cgd 			break;
    135   1.1       cgd 		case PCI_INTERRUPT_PIN_C:
    136   1.1       cgd 			pirq = 1;
    137   1.1       cgd 			break;
    138  1.12       cgd #ifdef DIAGNOSTIC
    139  1.12       cgd 		default:			/* XXX gcc -Wuninitialized */
    140  1.12       cgd 			panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
    141  1.12       cgd 			    buspin);
    142  1.12       cgd #endif
    143   1.1       cgd 		};
    144   1.1       cgd 		break;
    145   1.1       cgd 
    146   1.1       cgd 	case 12:				/* slot 2 */
    147   1.5       cgd 		switch (buspin) {
    148   1.1       cgd 		case PCI_INTERRUPT_PIN_A:
    149   1.1       cgd 		case PCI_INTERRUPT_PIN_D:
    150   1.1       cgd 			pirq = 1;
    151   1.1       cgd 			break;
    152   1.1       cgd 		case PCI_INTERRUPT_PIN_B:
    153   1.1       cgd 			pirq = 0;
    154   1.1       cgd 			break;
    155   1.1       cgd 		case PCI_INTERRUPT_PIN_C:
    156   1.1       cgd 			pirq = 2;
    157   1.1       cgd 			break;
    158  1.12       cgd #ifdef DIAGNOSTIC
    159  1.12       cgd 		default:			/* XXX gcc -Wuninitialized */
    160  1.12       cgd 			panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
    161  1.12       cgd 			    buspin);
    162  1.12       cgd #endif
    163   1.1       cgd 		};
    164   1.1       cgd 		break;
    165   1.1       cgd 
    166   1.1       cgd 	case 13:				/* slot 3 */
    167   1.5       cgd 		switch (buspin) {
    168   1.1       cgd 		case PCI_INTERRUPT_PIN_A:
    169   1.1       cgd 		case PCI_INTERRUPT_PIN_D:
    170   1.1       cgd 			pirq = 2;
    171   1.1       cgd 			break;
    172   1.1       cgd 		case PCI_INTERRUPT_PIN_B:
    173   1.1       cgd 			pirq = 1;
    174   1.1       cgd 			break;
    175   1.1       cgd 		case PCI_INTERRUPT_PIN_C:
    176   1.1       cgd 			pirq = 0;
    177   1.1       cgd 			break;
    178  1.12       cgd #ifdef DIAGNOSTIC
    179  1.12       cgd 		default:			/* XXX gcc -Wuninitialized */
    180  1.12       cgd 			panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
    181  1.12       cgd 			    buspin);
    182  1.12       cgd #endif
    183   1.1       cgd 		};
    184   1.1       cgd 		break;
    185  1.12       cgd 
    186  1.12       cgd 	default:
    187  1.12       cgd                 printf("dec_2100_a50_intr_map: weird device number %d\n",
    188  1.12       cgd 		    device);
    189  1.12       cgd                 return 1;
    190   1.1       cgd 	}
    191   1.1       cgd 
    192   1.7       cgd 	pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0),
    193   1.7       cgd 	    SIO_PCIREG_PIRQ_RTCTRL);
    194   1.1       cgd #if 0
    195  1.10  christos 	printf("pci_2100_a50_map_int: device %d pin %c: pirq %d, reg = %x\n",
    196   1.5       cgd 		device, '@' + buspin, pirq, pirqreg);
    197   1.1       cgd #endif
    198   1.3       cgd 	pirqline = (pirqreg >> (pirq * 8)) & 0xff;
    199   1.3       cgd 	if ((pirqline & 0x80) != 0)
    200   1.5       cgd 		return 1;
    201   1.3       cgd 	pirqline &= 0xf;
    202   1.1       cgd 
    203   1.1       cgd #if 0
    204  1.10  christos 	printf("pci_2100_a50_map_int: device %d pin %c: mapped to line %d\n",
    205   1.5       cgd 	    device, '@' + buspin, pirqline);
    206   1.1       cgd #endif
    207   1.1       cgd 
    208   1.5       cgd 	*ihp = pirqline;
    209   1.5       cgd 	return (0);
    210   1.3       cgd }
    211   1.3       cgd 
    212   1.5       cgd const char *
    213   1.5       cgd dec_2100_a50_intr_string(acv, ih)
    214   1.5       cgd 	void *acv;
    215   1.5       cgd 	pci_intr_handle_t ih;
    216   1.3       cgd {
    217  1.12       cgd #if 0
    218   1.5       cgd 	struct apecs_config *acp = acv;
    219  1.12       cgd #endif
    220   1.3       cgd 
    221   1.5       cgd 	return sio_intr_string(NULL /*XXX*/, ih);
    222   1.1       cgd }
    223   1.1       cgd 
    224   1.5       cgd void *
    225   1.5       cgd dec_2100_a50_intr_establish(acv, ih, level, func, arg)
    226   1.5       cgd 	void *acv, *arg;
    227   1.5       cgd 	pci_intr_handle_t ih;
    228   1.5       cgd 	int level;
    229   1.5       cgd 	int (*func) __P((void *));
    230   1.1       cgd {
    231  1.12       cgd #if 0
    232   1.5       cgd 	struct apecs_config *acp = acv;
    233  1.12       cgd #endif
    234   1.1       cgd 
    235   1.5       cgd 	return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func,
    236   1.5       cgd 	    arg);
    237   1.5       cgd }
    238   1.3       cgd 
    239   1.5       cgd void
    240   1.5       cgd dec_2100_a50_intr_disestablish(acv, cookie)
    241   1.5       cgd 	void *acv, *cookie;
    242   1.5       cgd {
    243  1.12       cgd #if 0
    244   1.5       cgd 	struct apecs_config *acp = acv;
    245  1.12       cgd #endif
    246   1.1       cgd 
    247   1.5       cgd 	sio_intr_disestablish(NULL /*XXX*/, cookie);
    248   1.1       cgd }
    249