pci_2100_a50.c revision 1.27 1 1.27 thorpej /* $NetBSD: pci_2100_a50.c,v 1.27 2000/06/05 21:47:22 thorpej Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.6 cgd * Copyright (c) 1995, 1996 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Author: Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.13 cgd
30 1.14 cgd #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
31 1.14 cgd
32 1.27 thorpej __KERNEL_RCSID(0, "$NetBSD: pci_2100_a50.c,v 1.27 2000/06/05 21:47:22 thorpej Exp $");
33 1.1 cgd
34 1.1 cgd #include <sys/types.h>
35 1.1 cgd #include <sys/param.h>
36 1.1 cgd #include <sys/time.h>
37 1.1 cgd #include <sys/systm.h>
38 1.1 cgd #include <sys/errno.h>
39 1.1 cgd #include <sys/device.h>
40 1.1 cgd #include <vm/vm.h>
41 1.1 cgd
42 1.8 cgd #include <machine/autoconf.h>
43 1.5 cgd #include <machine/bus.h>
44 1.5 cgd #include <machine/intr.h>
45 1.5 cgd
46 1.1 cgd #include <dev/isa/isavar.h>
47 1.3 cgd #include <dev/pci/pcireg.h>
48 1.1 cgd #include <dev/pci/pcivar.h>
49 1.1 cgd
50 1.3 cgd #include <alpha/pci/apecsvar.h>
51 1.1 cgd
52 1.3 cgd #include <alpha/pci/pci_2100_a50.h>
53 1.3 cgd #include <alpha/pci/siovar.h>
54 1.7 cgd #include <alpha/pci/sioreg.h>
55 1.1 cgd
56 1.3 cgd #include "sio.h"
57 1.1 cgd
58 1.5 cgd int dec_2100_a50_intr_map __P((void *, pcitag_t, int, int,
59 1.5 cgd pci_intr_handle_t *));
60 1.5 cgd const char *dec_2100_a50_intr_string __P((void *, pci_intr_handle_t));
61 1.26 cgd const struct evcnt *dec_2100_a50_intr_evcnt __P((void *, pci_intr_handle_t));
62 1.5 cgd void *dec_2100_a50_intr_establish __P((void *, pci_intr_handle_t,
63 1.5 cgd int, int (*func)(void *), void *));
64 1.5 cgd void dec_2100_a50_intr_disestablish __P((void *, void *));
65 1.5 cgd
66 1.7 cgd #define APECS_SIO_DEVICE 7 /* XXX */
67 1.7 cgd
68 1.5 cgd void
69 1.5 cgd pci_2100_a50_pickintr(acp)
70 1.5 cgd struct apecs_config *acp;
71 1.5 cgd {
72 1.18 thorpej bus_space_tag_t iot = &acp->ac_iot;
73 1.5 cgd pci_chipset_tag_t pc = &acp->ac_pc;
74 1.5 cgd pcireg_t sioclass;
75 1.5 cgd int sioII;
76 1.5 cgd
77 1.5 cgd /* XXX MAGIC NUMBER */
78 1.5 cgd sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG);
79 1.5 cgd sioII = (sioclass & 0xff) >= 3;
80 1.5 cgd
81 1.5 cgd if (!sioII)
82 1.10 christos printf("WARNING: SIO NOT SIO II... NO BETS...\n");
83 1.5 cgd
84 1.5 cgd pc->pc_intr_v = acp;
85 1.5 cgd pc->pc_intr_map = dec_2100_a50_intr_map;
86 1.5 cgd pc->pc_intr_string = dec_2100_a50_intr_string;
87 1.26 cgd pc->pc_intr_evcnt = dec_2100_a50_intr_evcnt;
88 1.5 cgd pc->pc_intr_establish = dec_2100_a50_intr_establish;
89 1.5 cgd pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish;
90 1.22 thorpej
91 1.23 mjacob /* Not supported on 2100 A50. */
92 1.22 thorpej pc->pc_pciide_compat_intr_establish = NULL;
93 1.1 cgd
94 1.5 cgd #if NSIO
95 1.20 thorpej sio_intr_setup(pc, iot);
96 1.5 cgd set_iointr(&sio_iointr);
97 1.5 cgd #else
98 1.5 cgd panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)");
99 1.5 cgd #endif
100 1.5 cgd }
101 1.5 cgd
102 1.5 cgd int
103 1.5 cgd dec_2100_a50_intr_map(acv, bustag, buspin, line, ihp)
104 1.3 cgd void *acv;
105 1.5 cgd pcitag_t bustag;
106 1.5 cgd int buspin, line;
107 1.5 cgd pci_intr_handle_t *ihp;
108 1.1 cgd {
109 1.3 cgd struct apecs_config *acp = acv;
110 1.5 cgd pci_chipset_tag_t pc = &acp->ac_pc;
111 1.5 cgd int device, pirq;
112 1.5 cgd pcireg_t pirqreg;
113 1.3 cgd u_int8_t pirqline;
114 1.15 cgd
115 1.15 cgd #ifndef DIAGNOSTIC
116 1.15 cgd pirq = 0; /* XXX gcc -Wuninitialized */
117 1.15 cgd #endif
118 1.1 cgd
119 1.24 thorpej if (buspin == 0) {
120 1.24 thorpej /* No IRQ used. */
121 1.24 thorpej return 1;
122 1.24 thorpej }
123 1.24 thorpej if (buspin > 4) {
124 1.24 thorpej printf("dec_2100_a50_intr_map: bad interrupt pin %d\n",
125 1.12 cgd buspin);
126 1.24 thorpej return 1;
127 1.24 thorpej }
128 1.1 cgd
129 1.16 cgd alpha_pci_decompose_tag(pc, bustag, NULL, &device, NULL);
130 1.1 cgd
131 1.1 cgd switch (device) {
132 1.1 cgd case 6: /* NCR SCSI */
133 1.1 cgd pirq = 3;
134 1.1 cgd break;
135 1.1 cgd
136 1.1 cgd case 11: /* slot 1 */
137 1.5 cgd case 14: /* slot 3 */
138 1.5 cgd switch (buspin) {
139 1.1 cgd case PCI_INTERRUPT_PIN_A:
140 1.1 cgd case PCI_INTERRUPT_PIN_D:
141 1.1 cgd pirq = 0;
142 1.1 cgd break;
143 1.1 cgd case PCI_INTERRUPT_PIN_B:
144 1.1 cgd pirq = 2;
145 1.1 cgd break;
146 1.1 cgd case PCI_INTERRUPT_PIN_C:
147 1.1 cgd pirq = 1;
148 1.1 cgd break;
149 1.12 cgd #ifdef DIAGNOSTIC
150 1.12 cgd default: /* XXX gcc -Wuninitialized */
151 1.12 cgd panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
152 1.12 cgd buspin);
153 1.12 cgd #endif
154 1.1 cgd };
155 1.1 cgd break;
156 1.1 cgd
157 1.1 cgd case 12: /* slot 2 */
158 1.5 cgd switch (buspin) {
159 1.1 cgd case PCI_INTERRUPT_PIN_A:
160 1.1 cgd case PCI_INTERRUPT_PIN_D:
161 1.1 cgd pirq = 1;
162 1.1 cgd break;
163 1.1 cgd case PCI_INTERRUPT_PIN_B:
164 1.1 cgd pirq = 0;
165 1.1 cgd break;
166 1.1 cgd case PCI_INTERRUPT_PIN_C:
167 1.1 cgd pirq = 2;
168 1.1 cgd break;
169 1.12 cgd #ifdef DIAGNOSTIC
170 1.12 cgd default: /* XXX gcc -Wuninitialized */
171 1.12 cgd panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
172 1.12 cgd buspin);
173 1.12 cgd #endif
174 1.1 cgd };
175 1.1 cgd break;
176 1.1 cgd
177 1.1 cgd case 13: /* slot 3 */
178 1.5 cgd switch (buspin) {
179 1.1 cgd case PCI_INTERRUPT_PIN_A:
180 1.1 cgd case PCI_INTERRUPT_PIN_D:
181 1.1 cgd pirq = 2;
182 1.1 cgd break;
183 1.1 cgd case PCI_INTERRUPT_PIN_B:
184 1.1 cgd pirq = 1;
185 1.1 cgd break;
186 1.1 cgd case PCI_INTERRUPT_PIN_C:
187 1.1 cgd pirq = 0;
188 1.1 cgd break;
189 1.12 cgd #ifdef DIAGNOSTIC
190 1.12 cgd default: /* XXX gcc -Wuninitialized */
191 1.12 cgd panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
192 1.12 cgd buspin);
193 1.12 cgd #endif
194 1.1 cgd };
195 1.1 cgd break;
196 1.12 cgd
197 1.12 cgd default:
198 1.12 cgd printf("dec_2100_a50_intr_map: weird device number %d\n",
199 1.12 cgd device);
200 1.12 cgd return 1;
201 1.1 cgd }
202 1.1 cgd
203 1.7 cgd pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0),
204 1.7 cgd SIO_PCIREG_PIRQ_RTCTRL);
205 1.1 cgd #if 0
206 1.21 thorpej printf("pci_2100_a50_intr_map: device %d pin %c: pirq %d, reg = %x\n",
207 1.5 cgd device, '@' + buspin, pirq, pirqreg);
208 1.1 cgd #endif
209 1.3 cgd pirqline = (pirqreg >> (pirq * 8)) & 0xff;
210 1.3 cgd if ((pirqline & 0x80) != 0)
211 1.5 cgd return 1;
212 1.3 cgd pirqline &= 0xf;
213 1.1 cgd
214 1.1 cgd #if 0
215 1.21 thorpej printf("pci_2100_a50_intr_map: device %d pin %c: mapped to line %d\n",
216 1.5 cgd device, '@' + buspin, pirqline);
217 1.1 cgd #endif
218 1.1 cgd
219 1.5 cgd *ihp = pirqline;
220 1.5 cgd return (0);
221 1.3 cgd }
222 1.3 cgd
223 1.5 cgd const char *
224 1.5 cgd dec_2100_a50_intr_string(acv, ih)
225 1.5 cgd void *acv;
226 1.5 cgd pci_intr_handle_t ih;
227 1.3 cgd {
228 1.12 cgd #if 0
229 1.5 cgd struct apecs_config *acp = acv;
230 1.12 cgd #endif
231 1.3 cgd
232 1.5 cgd return sio_intr_string(NULL /*XXX*/, ih);
233 1.26 cgd }
234 1.26 cgd
235 1.26 cgd const struct evcnt *
236 1.26 cgd dec_2100_a50_intr_evcnt(acv, ih)
237 1.26 cgd void *acv;
238 1.26 cgd pci_intr_handle_t ih;
239 1.26 cgd {
240 1.26 cgd #if 0
241 1.26 cgd struct apecs_config *acp = acv;
242 1.26 cgd #endif
243 1.26 cgd
244 1.26 cgd return sio_intr_evcnt(NULL /*XXX*/, ih);
245 1.1 cgd }
246 1.1 cgd
247 1.5 cgd void *
248 1.5 cgd dec_2100_a50_intr_establish(acv, ih, level, func, arg)
249 1.5 cgd void *acv, *arg;
250 1.5 cgd pci_intr_handle_t ih;
251 1.5 cgd int level;
252 1.5 cgd int (*func) __P((void *));
253 1.1 cgd {
254 1.12 cgd #if 0
255 1.5 cgd struct apecs_config *acp = acv;
256 1.12 cgd #endif
257 1.1 cgd
258 1.5 cgd return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func,
259 1.5 cgd arg);
260 1.5 cgd }
261 1.3 cgd
262 1.5 cgd void
263 1.5 cgd dec_2100_a50_intr_disestablish(acv, cookie)
264 1.5 cgd void *acv, *cookie;
265 1.5 cgd {
266 1.12 cgd #if 0
267 1.5 cgd struct apecs_config *acp = acv;
268 1.12 cgd #endif
269 1.1 cgd
270 1.5 cgd sio_intr_disestablish(NULL /*XXX*/, cookie);
271 1.1 cgd }
272