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pci_2100_a50.c revision 1.3
      1  1.3  cgd /*	$NetBSD: pci_2100_a50.c,v 1.3 1995/11/23 02:37:49 cgd Exp $	*/
      2  1.1  cgd 
      3  1.1  cgd /*
      4  1.2  cgd  * Copyright (c) 1995 Carnegie-Mellon University.
      5  1.1  cgd  * All rights reserved.
      6  1.1  cgd  *
      7  1.1  cgd  * Author: Chris G. Demetriou
      8  1.1  cgd  *
      9  1.1  cgd  * Permission to use, copy, modify and distribute this software and
     10  1.1  cgd  * its documentation is hereby granted, provided that both the copyright
     11  1.1  cgd  * notice and this permission notice appear in all copies of the
     12  1.1  cgd  * software, derivative works or modified versions, and any portions
     13  1.1  cgd  * thereof, and that both notices appear in supporting documentation.
     14  1.1  cgd  *
     15  1.1  cgd  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  1.1  cgd  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  1.1  cgd  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  1.1  cgd  *
     19  1.1  cgd  * Carnegie Mellon requests users of this software to return to
     20  1.1  cgd  *
     21  1.1  cgd  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  1.1  cgd  *  School of Computer Science
     23  1.1  cgd  *  Carnegie Mellon University
     24  1.1  cgd  *  Pittsburgh PA 15213-3890
     25  1.1  cgd  *
     26  1.1  cgd  * any improvements or extensions that they make and grant Carnegie the
     27  1.1  cgd  * rights to redistribute these changes.
     28  1.1  cgd  */
     29  1.1  cgd 
     30  1.1  cgd #include <sys/types.h>
     31  1.1  cgd #include <sys/param.h>
     32  1.1  cgd #include <sys/time.h>
     33  1.1  cgd #include <sys/systm.h>
     34  1.1  cgd #include <sys/errno.h>
     35  1.1  cgd #include <sys/device.h>
     36  1.1  cgd #include <vm/vm.h>
     37  1.1  cgd 
     38  1.1  cgd #include <dev/isa/isavar.h>
     39  1.3  cgd #include <dev/pci/pcireg.h>
     40  1.1  cgd #include <dev/pci/pcivar.h>
     41  1.1  cgd 
     42  1.3  cgd #include <alpha/pci/apecsvar.h>
     43  1.1  cgd 
     44  1.3  cgd #include <alpha/pci/pci_2100_a50.h>
     45  1.3  cgd #include <alpha/pci/siovar.h>
     46  1.1  cgd 
     47  1.3  cgd #include "sio.h"
     48  1.1  cgd 
     49  1.3  cgd void    *dec_2100_a50_pci_map_int __P((void *, pci_conftag_t,
     50  1.3  cgd 	    pci_intr_pin_t, pci_intr_line_t, pci_intrlevel_t,
     51  1.3  cgd 	    int (*func)(void *), void *));
     52  1.3  cgd void    dec_2100_a50_pci_unmap_int __P((void *, void *));
     53  1.1  cgd 
     54  1.3  cgd __const struct pci_intr_fns dec_2100_a50_pci_intr_fns = {
     55  1.3  cgd         dec_2100_a50_pci_map_int,
     56  1.3  cgd         dec_2100_a50_pci_unmap_int,
     57  1.3  cgd };
     58  1.1  cgd 
     59  1.1  cgd void *
     60  1.3  cgd dec_2100_a50_pci_map_int(acv, tag, pin, line, level, func, arg)
     61  1.3  cgd 	void *acv;
     62  1.3  cgd         pci_conftag_t tag;
     63  1.3  cgd 	pci_intr_pin_t pin;
     64  1.3  cgd 	pci_intr_line_t line;
     65  1.3  cgd         pci_intrlevel_t level;
     66  1.1  cgd         int (*func) __P((void *));
     67  1.1  cgd         void *arg;
     68  1.1  cgd {
     69  1.3  cgd 	struct apecs_config *acp = acv;
     70  1.1  cgd 	int bus, device, pirq;
     71  1.3  cgd 	pci_confreg_t irreg, pirqreg;
     72  1.3  cgd 	u_int8_t pirqline;
     73  1.1  cgd 
     74  1.3  cgd         if (pin == 0) {
     75  1.3  cgd                 /* No IRQ used. */
     76  1.3  cgd                 return 0;
     77  1.3  cgd         }
     78  1.3  cgd         if (pin > 4) {
     79  1.3  cgd                 printf("pci_map_int: bad interrupt pin %d\n", pin);
     80  1.3  cgd                 return NULL;
     81  1.3  cgd         }
     82  1.1  cgd 
     83  1.3  cgd 	device = PCI_TAG_DEVICE(tag);
     84  1.1  cgd 
     85  1.1  cgd 	switch (device) {
     86  1.1  cgd 	case 6:					/* NCR SCSI */
     87  1.1  cgd 		pirq = 3;
     88  1.1  cgd 		break;
     89  1.1  cgd 
     90  1.1  cgd 	case 11:				/* slot 1 */
     91  1.1  cgd 		switch (pin) {
     92  1.1  cgd 		case PCI_INTERRUPT_PIN_A:
     93  1.1  cgd 		case PCI_INTERRUPT_PIN_D:
     94  1.1  cgd 			pirq = 0;
     95  1.1  cgd 			break;
     96  1.1  cgd 		case PCI_INTERRUPT_PIN_B:
     97  1.1  cgd 			pirq = 2;
     98  1.1  cgd 			break;
     99  1.1  cgd 		case PCI_INTERRUPT_PIN_C:
    100  1.1  cgd 			pirq = 1;
    101  1.1  cgd 			break;
    102  1.1  cgd 		};
    103  1.1  cgd 		break;
    104  1.1  cgd 
    105  1.1  cgd 	case 12:				/* slot 2 */
    106  1.1  cgd 		switch (pin) {
    107  1.1  cgd 		case PCI_INTERRUPT_PIN_A:
    108  1.1  cgd 		case PCI_INTERRUPT_PIN_D:
    109  1.1  cgd 			pirq = 1;
    110  1.1  cgd 			break;
    111  1.1  cgd 		case PCI_INTERRUPT_PIN_B:
    112  1.1  cgd 			pirq = 0;
    113  1.1  cgd 			break;
    114  1.1  cgd 		case PCI_INTERRUPT_PIN_C:
    115  1.1  cgd 			pirq = 2;
    116  1.1  cgd 			break;
    117  1.1  cgd 		};
    118  1.1  cgd 		break;
    119  1.1  cgd 
    120  1.1  cgd 	case 13:				/* slot 3 */
    121  1.1  cgd 		switch (pin) {
    122  1.1  cgd 		case PCI_INTERRUPT_PIN_A:
    123  1.1  cgd 		case PCI_INTERRUPT_PIN_D:
    124  1.1  cgd 			pirq = 2;
    125  1.1  cgd 			break;
    126  1.1  cgd 		case PCI_INTERRUPT_PIN_B:
    127  1.1  cgd 			pirq = 1;
    128  1.1  cgd 			break;
    129  1.1  cgd 		case PCI_INTERRUPT_PIN_C:
    130  1.1  cgd 			pirq = 0;
    131  1.1  cgd 			break;
    132  1.1  cgd 		};
    133  1.1  cgd 		break;
    134  1.1  cgd 	}
    135  1.1  cgd 
    136  1.3  cgd 	pirqreg = PCI_CONF_READ(acp->ac_conffns, acp->ac_confarg,
    137  1.3  cgd 	    PCI_MAKE_TAG(0, 7, 0), 0x60); /* XXX */
    138  1.1  cgd #if 0
    139  1.1  cgd 	printf("pci_2100_a50_map_int: device %d pin %c: pirq %d, reg = %x\n",
    140  1.1  cgd 		device, '@' + pin, pirq, pirqreg);
    141  1.1  cgd #endif
    142  1.3  cgd 	pirqline = (pirqreg >> (pirq * 8)) & 0xff;
    143  1.3  cgd 	if ((pirqline & 0x80) != 0)
    144  1.1  cgd 		return 0;			/* not routed? */
    145  1.3  cgd 	pirqline &= 0xf;
    146  1.1  cgd 
    147  1.1  cgd #if 0
    148  1.1  cgd 	printf("pci_2100_a50_map_int: device %d pin %c: mapped to line %d\n",
    149  1.3  cgd 	    device, '@' + pin, pirqline);
    150  1.1  cgd #endif
    151  1.1  cgd 
    152  1.3  cgd #if NSIO
    153  1.3  cgd 	return ISA_INTR_ESTABLISH(&sio_isa_intr_fns, NULL,	/* XXX */
    154  1.3  cgd 	    pirqline, ISA_IST_LEVEL, pci_intrlevel_to_isa(level),
    155  1.1  cgd 	    func, arg);
    156  1.3  cgd #else
    157  1.3  cgd 	panic("dec_2100_a50_pci_map_int: no sio!");
    158  1.3  cgd #endif
    159  1.3  cgd }
    160  1.3  cgd 
    161  1.3  cgd void
    162  1.3  cgd dec_2100_a50_pci_unmap_int(pifa, cookie)
    163  1.3  cgd 	void *pifa;
    164  1.3  cgd 	void *cookie;
    165  1.3  cgd {
    166  1.3  cgd 
    167  1.3  cgd 	panic("dec_2100_a50_pci_unmap_int not implemented");	/* XXX */
    168  1.1  cgd }
    169  1.1  cgd 
    170  1.1  cgd void
    171  1.3  cgd pci_2100_a50_pickintr(pcf, pcfa, ppf, ppfa, pifp, pifap)
    172  1.3  cgd         __const struct pci_conf_fns *pcf;
    173  1.3  cgd         __const struct pci_pio_fns *ppf;
    174  1.3  cgd         void *pcfa, *ppfa;
    175  1.3  cgd         __const struct pci_intr_fns **pifp;
    176  1.3  cgd         void **pifap;
    177  1.1  cgd {
    178  1.3  cgd 	pci_confreg_t sioclass;
    179  1.1  cgd 	int sioII;
    180  1.1  cgd 
    181  1.1  cgd 	/* XXX MAGIC NUMBER */
    182  1.3  cgd 	sioclass = PCI_CONF_READ(pcf, pcfa, PCI_MAKE_TAG(0, 7, 0),
    183  1.3  cgd 	    PCI_CLASS_REG);
    184  1.1  cgd         sioII = (sioclass & 0xff) >= 3;
    185  1.3  cgd 
    186  1.1  cgd 	if (!sioII)
    187  1.1  cgd 		printf("WARNING: SIO NOT SIO II... NO BETS...\n");
    188  1.1  cgd 
    189  1.3  cgd 	*pifp = &dec_2100_a50_pci_intr_fns;
    190  1.3  cgd 	*pifap = pcfa;			/* XXX assumes apecs_config ptr */
    191  1.3  cgd #if NSIO
    192  1.3  cgd         sio_intr_setup(ppf, ppfa);
    193  1.3  cgd 	set_iointr(&sio_iointr);
    194  1.3  cgd #else
    195  1.3  cgd 	panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)");
    196  1.3  cgd #endif
    197  1.1  cgd }
    198