pci_2100_a50.c revision 1.30.2.2 1 1.30.2.2 nathanw /* $NetBSD: pci_2100_a50.c,v 1.30.2.2 2002/06/20 03:37:43 nathanw Exp $ */
2 1.30.2.2 nathanw
3 1.30.2.2 nathanw /*
4 1.30.2.2 nathanw * Copyright (c) 1995, 1996 Carnegie-Mellon University.
5 1.30.2.2 nathanw * All rights reserved.
6 1.30.2.2 nathanw *
7 1.30.2.2 nathanw * Author: Chris G. Demetriou
8 1.30.2.2 nathanw *
9 1.30.2.2 nathanw * Permission to use, copy, modify and distribute this software and
10 1.30.2.2 nathanw * its documentation is hereby granted, provided that both the copyright
11 1.30.2.2 nathanw * notice and this permission notice appear in all copies of the
12 1.30.2.2 nathanw * software, derivative works or modified versions, and any portions
13 1.30.2.2 nathanw * thereof, and that both notices appear in supporting documentation.
14 1.30.2.2 nathanw *
15 1.30.2.2 nathanw * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.30.2.2 nathanw * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.30.2.2 nathanw * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.30.2.2 nathanw *
19 1.30.2.2 nathanw * Carnegie Mellon requests users of this software to return to
20 1.30.2.2 nathanw *
21 1.30.2.2 nathanw * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.30.2.2 nathanw * School of Computer Science
23 1.30.2.2 nathanw * Carnegie Mellon University
24 1.30.2.2 nathanw * Pittsburgh PA 15213-3890
25 1.30.2.2 nathanw *
26 1.30.2.2 nathanw * any improvements or extensions that they make and grant Carnegie the
27 1.30.2.2 nathanw * rights to redistribute these changes.
28 1.30.2.2 nathanw */
29 1.30.2.2 nathanw
30 1.30.2.2 nathanw #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
31 1.30.2.2 nathanw
32 1.30.2.2 nathanw __KERNEL_RCSID(0, "$NetBSD: pci_2100_a50.c,v 1.30.2.2 2002/06/20 03:37:43 nathanw Exp $");
33 1.30.2.2 nathanw
34 1.30.2.2 nathanw #include <sys/types.h>
35 1.30.2.2 nathanw #include <sys/param.h>
36 1.30.2.2 nathanw #include <sys/time.h>
37 1.30.2.2 nathanw #include <sys/systm.h>
38 1.30.2.2 nathanw #include <sys/errno.h>
39 1.30.2.2 nathanw #include <sys/device.h>
40 1.30.2.2 nathanw
41 1.30.2.2 nathanw #include <uvm/uvm_extern.h>
42 1.30.2.2 nathanw
43 1.30.2.2 nathanw #include <machine/autoconf.h>
44 1.30.2.2 nathanw #include <machine/bus.h>
45 1.30.2.2 nathanw #include <machine/intr.h>
46 1.30.2.2 nathanw
47 1.30.2.2 nathanw #include <dev/isa/isavar.h>
48 1.30.2.2 nathanw #include <dev/pci/pcireg.h>
49 1.30.2.2 nathanw #include <dev/pci/pcivar.h>
50 1.30.2.2 nathanw
51 1.30.2.2 nathanw #include <alpha/pci/apecsvar.h>
52 1.30.2.2 nathanw
53 1.30.2.2 nathanw #include <alpha/pci/pci_2100_a50.h>
54 1.30.2.2 nathanw #include <alpha/pci/siovar.h>
55 1.30.2.2 nathanw #include <alpha/pci/sioreg.h>
56 1.30.2.2 nathanw
57 1.30.2.2 nathanw #include "sio.h"
58 1.30.2.2 nathanw
59 1.30.2.2 nathanw int dec_2100_a50_intr_map __P((struct pci_attach_args *, pci_intr_handle_t *));
60 1.30.2.2 nathanw const char *dec_2100_a50_intr_string __P((void *, pci_intr_handle_t));
61 1.30.2.2 nathanw const struct evcnt *dec_2100_a50_intr_evcnt __P((void *, pci_intr_handle_t));
62 1.30.2.2 nathanw void *dec_2100_a50_intr_establish __P((void *, pci_intr_handle_t,
63 1.30.2.2 nathanw int, int (*func)(void *), void *));
64 1.30.2.2 nathanw void dec_2100_a50_intr_disestablish __P((void *, void *));
65 1.30.2.2 nathanw
66 1.30.2.2 nathanw #define APECS_SIO_DEVICE 7 /* XXX */
67 1.30.2.2 nathanw
68 1.30.2.2 nathanw void
69 1.30.2.2 nathanw pci_2100_a50_pickintr(acp)
70 1.30.2.2 nathanw struct apecs_config *acp;
71 1.30.2.2 nathanw {
72 1.30.2.2 nathanw bus_space_tag_t iot = &acp->ac_iot;
73 1.30.2.2 nathanw pci_chipset_tag_t pc = &acp->ac_pc;
74 1.30.2.2 nathanw pcireg_t sioclass;
75 1.30.2.2 nathanw int sioII;
76 1.30.2.2 nathanw
77 1.30.2.2 nathanw /* XXX MAGIC NUMBER */
78 1.30.2.2 nathanw sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG);
79 1.30.2.2 nathanw sioII = (sioclass & 0xff) >= 3;
80 1.30.2.2 nathanw
81 1.30.2.2 nathanw if (!sioII)
82 1.30.2.2 nathanw printf("WARNING: SIO NOT SIO II... NO BETS...\n");
83 1.30.2.2 nathanw
84 1.30.2.2 nathanw pc->pc_intr_v = acp;
85 1.30.2.2 nathanw pc->pc_intr_map = dec_2100_a50_intr_map;
86 1.30.2.2 nathanw pc->pc_intr_string = dec_2100_a50_intr_string;
87 1.30.2.2 nathanw pc->pc_intr_evcnt = dec_2100_a50_intr_evcnt;
88 1.30.2.2 nathanw pc->pc_intr_establish = dec_2100_a50_intr_establish;
89 1.30.2.2 nathanw pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish;
90 1.30.2.2 nathanw
91 1.30.2.2 nathanw /* Not supported on 2100 A50. */
92 1.30.2.2 nathanw pc->pc_pciide_compat_intr_establish = NULL;
93 1.30.2.2 nathanw
94 1.30.2.2 nathanw #if NSIO
95 1.30.2.2 nathanw sio_intr_setup(pc, iot);
96 1.30.2.2 nathanw #else
97 1.30.2.2 nathanw panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)");
98 1.30.2.2 nathanw #endif
99 1.30.2.2 nathanw }
100 1.30.2.2 nathanw
101 1.30.2.2 nathanw int
102 1.30.2.2 nathanw dec_2100_a50_intr_map(pa, ihp)
103 1.30.2.2 nathanw struct pci_attach_args *pa;
104 1.30.2.2 nathanw pci_intr_handle_t *ihp;
105 1.30.2.2 nathanw {
106 1.30.2.2 nathanw pcitag_t bustag = pa->pa_intrtag;
107 1.30.2.2 nathanw int buspin = pa->pa_intrpin;
108 1.30.2.2 nathanw pci_chipset_tag_t pc = pa->pa_pc;
109 1.30.2.2 nathanw int device, pirq;
110 1.30.2.2 nathanw pcireg_t pirqreg;
111 1.30.2.2 nathanw u_int8_t pirqline;
112 1.30.2.2 nathanw
113 1.30.2.2 nathanw #ifndef DIAGNOSTIC
114 1.30.2.2 nathanw pirq = 0; /* XXX gcc -Wuninitialized */
115 1.30.2.2 nathanw #endif
116 1.30.2.2 nathanw
117 1.30.2.2 nathanw if (buspin == 0) {
118 1.30.2.2 nathanw /* No IRQ used. */
119 1.30.2.2 nathanw return 1;
120 1.30.2.2 nathanw }
121 1.30.2.2 nathanw if (buspin > 4) {
122 1.30.2.2 nathanw printf("dec_2100_a50_intr_map: bad interrupt pin %d\n",
123 1.30.2.2 nathanw buspin);
124 1.30.2.2 nathanw return 1;
125 1.30.2.2 nathanw }
126 1.30.2.2 nathanw
127 1.30.2.2 nathanw pci_decompose_tag(pc, bustag, NULL, &device, NULL);
128 1.30.2.2 nathanw
129 1.30.2.2 nathanw switch (device) {
130 1.30.2.2 nathanw case 6: /* NCR SCSI */
131 1.30.2.2 nathanw pirq = 3;
132 1.30.2.2 nathanw break;
133 1.30.2.2 nathanw
134 1.30.2.2 nathanw case 11: /* slot 1 */
135 1.30.2.2 nathanw case 14: /* slot 3 */
136 1.30.2.2 nathanw switch (buspin) {
137 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_A:
138 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_D:
139 1.30.2.2 nathanw pirq = 0;
140 1.30.2.2 nathanw break;
141 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_B:
142 1.30.2.2 nathanw pirq = 2;
143 1.30.2.2 nathanw break;
144 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_C:
145 1.30.2.2 nathanw pirq = 1;
146 1.30.2.2 nathanw break;
147 1.30.2.2 nathanw #ifdef DIAGNOSTIC
148 1.30.2.2 nathanw default: /* XXX gcc -Wuninitialized */
149 1.30.2.2 nathanw panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
150 1.30.2.2 nathanw buspin);
151 1.30.2.2 nathanw #endif
152 1.30.2.2 nathanw };
153 1.30.2.2 nathanw break;
154 1.30.2.2 nathanw
155 1.30.2.2 nathanw case 12: /* slot 2 */
156 1.30.2.2 nathanw switch (buspin) {
157 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_A:
158 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_D:
159 1.30.2.2 nathanw pirq = 1;
160 1.30.2.2 nathanw break;
161 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_B:
162 1.30.2.2 nathanw pirq = 0;
163 1.30.2.2 nathanw break;
164 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_C:
165 1.30.2.2 nathanw pirq = 2;
166 1.30.2.2 nathanw break;
167 1.30.2.2 nathanw #ifdef DIAGNOSTIC
168 1.30.2.2 nathanw default: /* XXX gcc -Wuninitialized */
169 1.30.2.2 nathanw panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
170 1.30.2.2 nathanw buspin);
171 1.30.2.2 nathanw #endif
172 1.30.2.2 nathanw };
173 1.30.2.2 nathanw break;
174 1.30.2.2 nathanw
175 1.30.2.2 nathanw case 13: /* slot 3 */
176 1.30.2.2 nathanw switch (buspin) {
177 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_A:
178 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_D:
179 1.30.2.2 nathanw pirq = 2;
180 1.30.2.2 nathanw break;
181 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_B:
182 1.30.2.2 nathanw pirq = 1;
183 1.30.2.2 nathanw break;
184 1.30.2.2 nathanw case PCI_INTERRUPT_PIN_C:
185 1.30.2.2 nathanw pirq = 0;
186 1.30.2.2 nathanw break;
187 1.30.2.2 nathanw #ifdef DIAGNOSTIC
188 1.30.2.2 nathanw default: /* XXX gcc -Wuninitialized */
189 1.30.2.2 nathanw panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
190 1.30.2.2 nathanw buspin);
191 1.30.2.2 nathanw #endif
192 1.30.2.2 nathanw };
193 1.30.2.2 nathanw break;
194 1.30.2.2 nathanw
195 1.30.2.2 nathanw default:
196 1.30.2.2 nathanw printf("dec_2100_a50_intr_map: weird device number %d\n",
197 1.30.2.2 nathanw device);
198 1.30.2.2 nathanw return 1;
199 1.30.2.2 nathanw }
200 1.30.2.2 nathanw
201 1.30.2.2 nathanw pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0),
202 1.30.2.2 nathanw SIO_PCIREG_PIRQ_RTCTRL);
203 1.30.2.2 nathanw #if 0
204 1.30.2.2 nathanw printf("pci_2100_a50_intr_map: device %d pin %c: pirq %d, reg = %x\n",
205 1.30.2.2 nathanw device, '@' + buspin, pirq, pirqreg);
206 1.30.2.2 nathanw #endif
207 1.30.2.2 nathanw pirqline = (pirqreg >> (pirq * 8)) & 0xff;
208 1.30.2.2 nathanw if ((pirqline & 0x80) != 0)
209 1.30.2.2 nathanw return 1;
210 1.30.2.2 nathanw pirqline &= 0xf;
211 1.30.2.2 nathanw
212 1.30.2.2 nathanw #if 0
213 1.30.2.2 nathanw printf("pci_2100_a50_intr_map: device %d pin %c: mapped to line %d\n",
214 1.30.2.2 nathanw device, '@' + buspin, pirqline);
215 1.30.2.2 nathanw #endif
216 1.30.2.2 nathanw
217 1.30.2.2 nathanw *ihp = pirqline;
218 1.30.2.2 nathanw return (0);
219 1.30.2.2 nathanw }
220 1.30.2.2 nathanw
221 1.30.2.2 nathanw const char *
222 1.30.2.2 nathanw dec_2100_a50_intr_string(acv, ih)
223 1.30.2.2 nathanw void *acv;
224 1.30.2.2 nathanw pci_intr_handle_t ih;
225 1.30.2.2 nathanw {
226 1.30.2.2 nathanw #if 0
227 1.30.2.2 nathanw struct apecs_config *acp = acv;
228 1.30.2.2 nathanw #endif
229 1.30.2.2 nathanw
230 1.30.2.2 nathanw return sio_intr_string(NULL /*XXX*/, ih);
231 1.30.2.2 nathanw }
232 1.30.2.2 nathanw
233 1.30.2.2 nathanw const struct evcnt *
234 1.30.2.2 nathanw dec_2100_a50_intr_evcnt(acv, ih)
235 1.30.2.2 nathanw void *acv;
236 1.30.2.2 nathanw pci_intr_handle_t ih;
237 1.30.2.2 nathanw {
238 1.30.2.2 nathanw #if 0
239 1.30.2.2 nathanw struct apecs_config *acp = acv;
240 1.30.2.2 nathanw #endif
241 1.30.2.2 nathanw
242 1.30.2.2 nathanw return sio_intr_evcnt(NULL /*XXX*/, ih);
243 1.30.2.2 nathanw }
244 1.30.2.2 nathanw
245 1.30.2.2 nathanw void *
246 1.30.2.2 nathanw dec_2100_a50_intr_establish(acv, ih, level, func, arg)
247 1.30.2.2 nathanw void *acv, *arg;
248 1.30.2.2 nathanw pci_intr_handle_t ih;
249 1.30.2.2 nathanw int level;
250 1.30.2.2 nathanw int (*func) __P((void *));
251 1.30.2.2 nathanw {
252 1.30.2.2 nathanw #if 0
253 1.30.2.2 nathanw struct apecs_config *acp = acv;
254 1.30.2.2 nathanw #endif
255 1.30.2.2 nathanw
256 1.30.2.2 nathanw return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func,
257 1.30.2.2 nathanw arg);
258 1.30.2.2 nathanw }
259 1.30.2.2 nathanw
260 1.30.2.2 nathanw void
261 1.30.2.2 nathanw dec_2100_a50_intr_disestablish(acv, cookie)
262 1.30.2.2 nathanw void *acv, *cookie;
263 1.30.2.2 nathanw {
264 1.30.2.2 nathanw #if 0
265 1.30.2.2 nathanw struct apecs_config *acp = acv;
266 1.30.2.2 nathanw #endif
267 1.30.2.2 nathanw
268 1.30.2.2 nathanw sio_intr_disestablish(NULL /*XXX*/, cookie);
269 1.30.2.2 nathanw }
270