pci_2100_a50.c revision 1.40 1 1.40 matt /* $NetBSD: pci_2100_a50.c,v 1.40 2012/02/06 02:14:15 matt Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.6 cgd * Copyright (c) 1995, 1996 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Author: Chris G. Demetriou
8 1.40 matt *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.40 matt *
15 1.40 matt * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.40 matt * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.40 matt *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.13 cgd
30 1.14 cgd #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
31 1.14 cgd
32 1.40 matt __KERNEL_RCSID(0, "$NetBSD: pci_2100_a50.c,v 1.40 2012/02/06 02:14:15 matt Exp $");
33 1.1 cgd
34 1.1 cgd #include <sys/types.h>
35 1.1 cgd #include <sys/param.h>
36 1.1 cgd #include <sys/time.h>
37 1.1 cgd #include <sys/systm.h>
38 1.1 cgd #include <sys/errno.h>
39 1.1 cgd #include <sys/device.h>
40 1.28 mrg
41 1.8 cgd #include <machine/autoconf.h>
42 1.39 dyoung #include <sys/bus.h>
43 1.5 cgd #include <machine/intr.h>
44 1.5 cgd
45 1.1 cgd #include <dev/isa/isavar.h>
46 1.3 cgd #include <dev/pci/pcireg.h>
47 1.1 cgd #include <dev/pci/pcivar.h>
48 1.1 cgd
49 1.3 cgd #include <alpha/pci/apecsvar.h>
50 1.1 cgd
51 1.3 cgd #include <alpha/pci/pci_2100_a50.h>
52 1.3 cgd #include <alpha/pci/siovar.h>
53 1.7 cgd #include <alpha/pci/sioreg.h>
54 1.1 cgd
55 1.3 cgd #include "sio.h"
56 1.1 cgd
57 1.38 dyoung int dec_2100_a50_intr_map(const struct pci_attach_args *,
58 1.38 dyoung pci_intr_handle_t *);
59 1.33 dsl const char *dec_2100_a50_intr_string(void *, pci_intr_handle_t);
60 1.33 dsl const struct evcnt *dec_2100_a50_intr_evcnt(void *, pci_intr_handle_t);
61 1.33 dsl void *dec_2100_a50_intr_establish(void *, pci_intr_handle_t,
62 1.33 dsl int, int (*func)(void *), void *);
63 1.33 dsl void dec_2100_a50_intr_disestablish(void *, void *);
64 1.5 cgd
65 1.7 cgd #define APECS_SIO_DEVICE 7 /* XXX */
66 1.7 cgd
67 1.5 cgd void
68 1.34 dsl pci_2100_a50_pickintr(struct apecs_config *acp)
69 1.5 cgd {
70 1.18 thorpej bus_space_tag_t iot = &acp->ac_iot;
71 1.5 cgd pci_chipset_tag_t pc = &acp->ac_pc;
72 1.5 cgd pcireg_t sioclass;
73 1.5 cgd int sioII;
74 1.5 cgd
75 1.5 cgd /* XXX MAGIC NUMBER */
76 1.5 cgd sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG);
77 1.40 matt sioII = (sioclass & 0xff) >= 3;
78 1.5 cgd
79 1.5 cgd if (!sioII)
80 1.10 christos printf("WARNING: SIO NOT SIO II... NO BETS...\n");
81 1.5 cgd
82 1.5 cgd pc->pc_intr_v = acp;
83 1.5 cgd pc->pc_intr_map = dec_2100_a50_intr_map;
84 1.5 cgd pc->pc_intr_string = dec_2100_a50_intr_string;
85 1.26 cgd pc->pc_intr_evcnt = dec_2100_a50_intr_evcnt;
86 1.5 cgd pc->pc_intr_establish = dec_2100_a50_intr_establish;
87 1.5 cgd pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish;
88 1.22 thorpej
89 1.23 mjacob /* Not supported on 2100 A50. */
90 1.22 thorpej pc->pc_pciide_compat_intr_establish = NULL;
91 1.1 cgd
92 1.5 cgd #if NSIO
93 1.20 thorpej sio_intr_setup(pc, iot);
94 1.5 cgd #else
95 1.5 cgd panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)");
96 1.5 cgd #endif
97 1.5 cgd }
98 1.5 cgd
99 1.5 cgd int
100 1.38 dyoung dec_2100_a50_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
101 1.1 cgd {
102 1.40 matt pcitag_t bustag = pa->pa_intrtag;
103 1.29 sommerfe int buspin = pa->pa_intrpin;
104 1.29 sommerfe pci_chipset_tag_t pc = pa->pa_pc;
105 1.5 cgd int device, pirq;
106 1.5 cgd pcireg_t pirqreg;
107 1.40 matt uint8_t pirqline;
108 1.15 cgd
109 1.15 cgd #ifndef DIAGNOSTIC
110 1.15 cgd pirq = 0; /* XXX gcc -Wuninitialized */
111 1.15 cgd #endif
112 1.1 cgd
113 1.24 thorpej if (buspin == 0) {
114 1.24 thorpej /* No IRQ used. */
115 1.24 thorpej return 1;
116 1.24 thorpej }
117 1.24 thorpej if (buspin > 4) {
118 1.24 thorpej printf("dec_2100_a50_intr_map: bad interrupt pin %d\n",
119 1.12 cgd buspin);
120 1.24 thorpej return 1;
121 1.24 thorpej }
122 1.1 cgd
123 1.31 thorpej pci_decompose_tag(pc, bustag, NULL, &device, NULL);
124 1.1 cgd
125 1.1 cgd switch (device) {
126 1.1 cgd case 6: /* NCR SCSI */
127 1.1 cgd pirq = 3;
128 1.1 cgd break;
129 1.1 cgd
130 1.1 cgd case 11: /* slot 1 */
131 1.5 cgd case 14: /* slot 3 */
132 1.5 cgd switch (buspin) {
133 1.1 cgd case PCI_INTERRUPT_PIN_A:
134 1.1 cgd case PCI_INTERRUPT_PIN_D:
135 1.1 cgd pirq = 0;
136 1.1 cgd break;
137 1.1 cgd case PCI_INTERRUPT_PIN_B:
138 1.1 cgd pirq = 2;
139 1.1 cgd break;
140 1.1 cgd case PCI_INTERRUPT_PIN_C:
141 1.1 cgd pirq = 1;
142 1.1 cgd break;
143 1.12 cgd #ifdef DIAGNOSTIC
144 1.12 cgd default: /* XXX gcc -Wuninitialized */
145 1.32 provos panic("dec_2100_a50_intr_map bogus PCI pin %d",
146 1.12 cgd buspin);
147 1.12 cgd #endif
148 1.1 cgd };
149 1.1 cgd break;
150 1.1 cgd
151 1.1 cgd case 12: /* slot 2 */
152 1.5 cgd switch (buspin) {
153 1.1 cgd case PCI_INTERRUPT_PIN_A:
154 1.1 cgd case PCI_INTERRUPT_PIN_D:
155 1.1 cgd pirq = 1;
156 1.1 cgd break;
157 1.1 cgd case PCI_INTERRUPT_PIN_B:
158 1.1 cgd pirq = 0;
159 1.1 cgd break;
160 1.1 cgd case PCI_INTERRUPT_PIN_C:
161 1.1 cgd pirq = 2;
162 1.1 cgd break;
163 1.12 cgd #ifdef DIAGNOSTIC
164 1.12 cgd default: /* XXX gcc -Wuninitialized */
165 1.32 provos panic("dec_2100_a50_intr_map bogus PCI pin %d",
166 1.12 cgd buspin);
167 1.12 cgd #endif
168 1.1 cgd };
169 1.1 cgd break;
170 1.1 cgd
171 1.1 cgd case 13: /* slot 3 */
172 1.5 cgd switch (buspin) {
173 1.1 cgd case PCI_INTERRUPT_PIN_A:
174 1.1 cgd case PCI_INTERRUPT_PIN_D:
175 1.1 cgd pirq = 2;
176 1.1 cgd break;
177 1.1 cgd case PCI_INTERRUPT_PIN_B:
178 1.1 cgd pirq = 1;
179 1.1 cgd break;
180 1.1 cgd case PCI_INTERRUPT_PIN_C:
181 1.1 cgd pirq = 0;
182 1.1 cgd break;
183 1.12 cgd #ifdef DIAGNOSTIC
184 1.12 cgd default: /* XXX gcc -Wuninitialized */
185 1.32 provos panic("dec_2100_a50_intr_map bogus PCI pin %d",
186 1.12 cgd buspin);
187 1.12 cgd #endif
188 1.1 cgd };
189 1.1 cgd break;
190 1.12 cgd
191 1.12 cgd default:
192 1.40 matt printf("dec_2100_a50_intr_map: weird device number %d\n",
193 1.12 cgd device);
194 1.40 matt return 1;
195 1.1 cgd }
196 1.1 cgd
197 1.7 cgd pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0),
198 1.7 cgd SIO_PCIREG_PIRQ_RTCTRL);
199 1.1 cgd #if 0
200 1.21 thorpej printf("pci_2100_a50_intr_map: device %d pin %c: pirq %d, reg = %x\n",
201 1.5 cgd device, '@' + buspin, pirq, pirqreg);
202 1.1 cgd #endif
203 1.3 cgd pirqline = (pirqreg >> (pirq * 8)) & 0xff;
204 1.3 cgd if ((pirqline & 0x80) != 0)
205 1.5 cgd return 1;
206 1.3 cgd pirqline &= 0xf;
207 1.1 cgd
208 1.1 cgd #if 0
209 1.21 thorpej printf("pci_2100_a50_intr_map: device %d pin %c: mapped to line %d\n",
210 1.5 cgd device, '@' + buspin, pirqline);
211 1.1 cgd #endif
212 1.1 cgd
213 1.5 cgd *ihp = pirqline;
214 1.5 cgd return (0);
215 1.3 cgd }
216 1.3 cgd
217 1.5 cgd const char *
218 1.34 dsl dec_2100_a50_intr_string(void *acv, pci_intr_handle_t ih)
219 1.3 cgd {
220 1.12 cgd #if 0
221 1.5 cgd struct apecs_config *acp = acv;
222 1.12 cgd #endif
223 1.3 cgd
224 1.5 cgd return sio_intr_string(NULL /*XXX*/, ih);
225 1.26 cgd }
226 1.26 cgd
227 1.26 cgd const struct evcnt *
228 1.34 dsl dec_2100_a50_intr_evcnt(void *acv, pci_intr_handle_t ih)
229 1.26 cgd {
230 1.26 cgd #if 0
231 1.26 cgd struct apecs_config *acp = acv;
232 1.26 cgd #endif
233 1.26 cgd
234 1.26 cgd return sio_intr_evcnt(NULL /*XXX*/, ih);
235 1.1 cgd }
236 1.1 cgd
237 1.5 cgd void *
238 1.36 dsl dec_2100_a50_intr_establish(void *acv, pci_intr_handle_t ih, int level, int (*func)(void *), void *arg)
239 1.1 cgd {
240 1.12 cgd #if 0
241 1.5 cgd struct apecs_config *acp = acv;
242 1.12 cgd #endif
243 1.1 cgd
244 1.5 cgd return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func,
245 1.5 cgd arg);
246 1.5 cgd }
247 1.3 cgd
248 1.5 cgd void
249 1.35 dsl dec_2100_a50_intr_disestablish(void *acv, void *cookie)
250 1.5 cgd {
251 1.12 cgd #if 0
252 1.5 cgd struct apecs_config *acp = acv;
253 1.12 cgd #endif
254 1.1 cgd
255 1.5 cgd sio_intr_disestablish(NULL /*XXX*/, cookie);
256 1.1 cgd }
257