pci_2100_a50.c revision 1.6 1 1.6 cgd /* $NetBSD: pci_2100_a50.c,v 1.6 1996/04/12 06:08:37 cgd Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.6 cgd * Copyright (c) 1995, 1996 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Author: Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.1 cgd
30 1.1 cgd #include <sys/types.h>
31 1.1 cgd #include <sys/param.h>
32 1.1 cgd #include <sys/time.h>
33 1.1 cgd #include <sys/systm.h>
34 1.1 cgd #include <sys/errno.h>
35 1.1 cgd #include <sys/device.h>
36 1.1 cgd #include <vm/vm.h>
37 1.1 cgd
38 1.5 cgd #include <machine/bus.h>
39 1.5 cgd #include <machine/intr.h>
40 1.5 cgd
41 1.1 cgd #include <dev/isa/isavar.h>
42 1.3 cgd #include <dev/pci/pcireg.h>
43 1.1 cgd #include <dev/pci/pcivar.h>
44 1.1 cgd
45 1.3 cgd #include <alpha/pci/apecsvar.h>
46 1.1 cgd
47 1.3 cgd #include <alpha/pci/pci_2100_a50.h>
48 1.3 cgd #include <alpha/pci/siovar.h>
49 1.1 cgd
50 1.3 cgd #include "sio.h"
51 1.1 cgd
52 1.5 cgd int dec_2100_a50_intr_map __P((void *, pcitag_t, int, int,
53 1.5 cgd pci_intr_handle_t *));
54 1.5 cgd const char *dec_2100_a50_intr_string __P((void *, pci_intr_handle_t));
55 1.5 cgd void *dec_2100_a50_intr_establish __P((void *, pci_intr_handle_t,
56 1.5 cgd int, int (*func)(void *), void *));
57 1.5 cgd void dec_2100_a50_intr_disestablish __P((void *, void *));
58 1.5 cgd
59 1.5 cgd void
60 1.5 cgd pci_2100_a50_pickintr(acp)
61 1.5 cgd struct apecs_config *acp;
62 1.5 cgd {
63 1.5 cgd bus_chipset_tag_t bc = &acp->ac_bc;
64 1.5 cgd pci_chipset_tag_t pc = &acp->ac_pc;
65 1.5 cgd pcireg_t sioclass;
66 1.5 cgd int sioII;
67 1.5 cgd
68 1.5 cgd /* XXX MAGIC NUMBER */
69 1.5 cgd sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG);
70 1.5 cgd sioII = (sioclass & 0xff) >= 3;
71 1.5 cgd
72 1.5 cgd if (!sioII)
73 1.5 cgd printf("WARNING: SIO NOT SIO II... NO BETS...\n");
74 1.5 cgd
75 1.5 cgd pc->pc_intr_v = acp;
76 1.5 cgd pc->pc_intr_map = dec_2100_a50_intr_map;
77 1.5 cgd pc->pc_intr_string = dec_2100_a50_intr_string;
78 1.5 cgd pc->pc_intr_establish = dec_2100_a50_intr_establish;
79 1.5 cgd pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish;
80 1.1 cgd
81 1.5 cgd #if NSIO
82 1.5 cgd sio_intr_setup(bc);
83 1.5 cgd set_iointr(&sio_iointr);
84 1.5 cgd #else
85 1.5 cgd panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)");
86 1.5 cgd #endif
87 1.5 cgd }
88 1.5 cgd
89 1.5 cgd int
90 1.5 cgd dec_2100_a50_intr_map(acv, bustag, buspin, line, ihp)
91 1.3 cgd void *acv;
92 1.5 cgd pcitag_t bustag;
93 1.5 cgd int buspin, line;
94 1.5 cgd pci_intr_handle_t *ihp;
95 1.1 cgd {
96 1.3 cgd struct apecs_config *acp = acv;
97 1.5 cgd pci_chipset_tag_t pc = &acp->ac_pc;
98 1.5 cgd int device, pirq;
99 1.5 cgd pcireg_t pirqreg;
100 1.3 cgd u_int8_t pirqline;
101 1.1 cgd
102 1.5 cgd if (buspin == 0) {
103 1.3 cgd /* No IRQ used. */
104 1.5 cgd return 1;
105 1.3 cgd }
106 1.5 cgd if (buspin > 4) {
107 1.5 cgd printf("pci_map_int: bad interrupt pin %d\n", buspin);
108 1.5 cgd return 1;
109 1.3 cgd }
110 1.1 cgd
111 1.5 cgd pci_decompose_tag(pc, bustag, NULL, &device, NULL);
112 1.1 cgd
113 1.1 cgd switch (device) {
114 1.1 cgd case 6: /* NCR SCSI */
115 1.1 cgd pirq = 3;
116 1.1 cgd break;
117 1.1 cgd
118 1.1 cgd case 11: /* slot 1 */
119 1.5 cgd case 14: /* slot 3 */
120 1.5 cgd switch (buspin) {
121 1.1 cgd case PCI_INTERRUPT_PIN_A:
122 1.1 cgd case PCI_INTERRUPT_PIN_D:
123 1.1 cgd pirq = 0;
124 1.1 cgd break;
125 1.1 cgd case PCI_INTERRUPT_PIN_B:
126 1.1 cgd pirq = 2;
127 1.1 cgd break;
128 1.1 cgd case PCI_INTERRUPT_PIN_C:
129 1.1 cgd pirq = 1;
130 1.1 cgd break;
131 1.1 cgd };
132 1.1 cgd break;
133 1.1 cgd
134 1.1 cgd case 12: /* slot 2 */
135 1.5 cgd switch (buspin) {
136 1.1 cgd case PCI_INTERRUPT_PIN_A:
137 1.1 cgd case PCI_INTERRUPT_PIN_D:
138 1.1 cgd pirq = 1;
139 1.1 cgd break;
140 1.1 cgd case PCI_INTERRUPT_PIN_B:
141 1.1 cgd pirq = 0;
142 1.1 cgd break;
143 1.1 cgd case PCI_INTERRUPT_PIN_C:
144 1.1 cgd pirq = 2;
145 1.1 cgd break;
146 1.1 cgd };
147 1.1 cgd break;
148 1.1 cgd
149 1.1 cgd case 13: /* slot 3 */
150 1.5 cgd switch (buspin) {
151 1.1 cgd case PCI_INTERRUPT_PIN_A:
152 1.1 cgd case PCI_INTERRUPT_PIN_D:
153 1.1 cgd pirq = 2;
154 1.1 cgd break;
155 1.1 cgd case PCI_INTERRUPT_PIN_B:
156 1.1 cgd pirq = 1;
157 1.1 cgd break;
158 1.1 cgd case PCI_INTERRUPT_PIN_C:
159 1.1 cgd pirq = 0;
160 1.1 cgd break;
161 1.1 cgd };
162 1.1 cgd break;
163 1.1 cgd }
164 1.1 cgd
165 1.5 cgd pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), 0x60); /*XXX*/
166 1.1 cgd #if 0
167 1.1 cgd printf("pci_2100_a50_map_int: device %d pin %c: pirq %d, reg = %x\n",
168 1.5 cgd device, '@' + buspin, pirq, pirqreg);
169 1.1 cgd #endif
170 1.3 cgd pirqline = (pirqreg >> (pirq * 8)) & 0xff;
171 1.3 cgd if ((pirqline & 0x80) != 0)
172 1.5 cgd return 1;
173 1.3 cgd pirqline &= 0xf;
174 1.1 cgd
175 1.1 cgd #if 0
176 1.1 cgd printf("pci_2100_a50_map_int: device %d pin %c: mapped to line %d\n",
177 1.5 cgd device, '@' + buspin, pirqline);
178 1.1 cgd #endif
179 1.1 cgd
180 1.5 cgd *ihp = pirqline;
181 1.5 cgd return (0);
182 1.3 cgd }
183 1.3 cgd
184 1.5 cgd const char *
185 1.5 cgd dec_2100_a50_intr_string(acv, ih)
186 1.5 cgd void *acv;
187 1.5 cgd pci_intr_handle_t ih;
188 1.3 cgd {
189 1.5 cgd struct apecs_config *acp = acv;
190 1.3 cgd
191 1.5 cgd return sio_intr_string(NULL /*XXX*/, ih);
192 1.1 cgd }
193 1.1 cgd
194 1.5 cgd void *
195 1.5 cgd dec_2100_a50_intr_establish(acv, ih, level, func, arg)
196 1.5 cgd void *acv, *arg;
197 1.5 cgd pci_intr_handle_t ih;
198 1.5 cgd int level;
199 1.5 cgd int (*func) __P((void *));
200 1.1 cgd {
201 1.5 cgd struct apecs_config *acp = acv;
202 1.1 cgd
203 1.5 cgd return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func,
204 1.5 cgd arg);
205 1.5 cgd }
206 1.3 cgd
207 1.5 cgd void
208 1.5 cgd dec_2100_a50_intr_disestablish(acv, cookie)
209 1.5 cgd void *acv, *cookie;
210 1.5 cgd {
211 1.5 cgd struct apecs_config *acp = acv;
212 1.1 cgd
213 1.5 cgd sio_intr_disestablish(NULL /*XXX*/, cookie);
214 1.1 cgd }
215