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pci_2100_a50.c revision 1.1 
      1 /*	$NetBSD: pci_2100_a50.c,v 1.1 1995/06/28 01:25:43 cgd Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1994, 1995 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 #include <sys/types.h>
     31 #include <sys/param.h>
     32 #include <sys/time.h>
     33 #include <sys/systm.h>
     34 #include <sys/errno.h>
     35 #include <sys/device.h>
     36 
     37 #include <vm/vm.h>
     38 
     39 #include <dev/isa/isavar.h>
     40 #include <alpha/isa/isa_intr.h>
     41 
     42 #include <dev/pci/pcivar.h>
     43 #include <dev/pci/pcireg.h>
     44 #include <alpha/pci/pci_chipset.h>
     45 
     46 void	pci_2100_a50_attach __P((struct device *, struct device *, void *));
     47 void	*pci_2100_a50_map_int __P((pcitag_t, pci_intrlevel, int (*) (void *),
     48 	    void *, int));
     49 
     50 struct pci_cfg_fcns pci_2100_a50_sio1_cfg_fcns = {	/* XXX diff? */
     51 	pci_2100_a50_attach, pci_2100_a50_map_int,
     52 };
     53 
     54 struct pci_cfg_fcns pci_2100_a50_sio2_cfg_fcns = {
     55 	pci_2100_a50_attach, pci_2100_a50_map_int,
     56 };
     57 
     58 void
     59 pci_2100_a50_attach(parent, self, aux)
     60         struct device *parent, *self;
     61         void *aux;
     62 {
     63 	int bus, device;
     64 
     65 #if 0
     66 	for (bus = 0; bus <= 255; bus++)
     67 #else
     68 	/*
     69 	 * XXX
     70 	 * Some current chipsets do wacky things with bus numbers > 0.
     71 	 * This seems like a violation of protocol, but the PCI BIOS does
     72 	 * allow one to query the maximum bus number, and eventually we
     73 	 * should do so.
     74 	 */
     75 	for (bus = 0; bus <= 0; bus++)
     76 #endif
     77 		for (device = 0; device <= 31; device++)
     78 			pci_attach_subdev(self, bus, device);
     79 }
     80 
     81 void *
     82 pci_2100_a50_map_int(tag, level, func, arg, pin)
     83         pcitag_t tag;
     84         pci_intrlevel level;
     85         int (*func) __P((void *));
     86         void *arg;
     87 	int pin;
     88 {
     89 	int bus, device, pirq;
     90 	pcireg_t pirqreg;
     91 	u_int8_t line;
     92 
     93 	bus = (tag >> 21) & 0xff;		/* XXX */
     94 	device = (tag >> 16) & 0x1f;
     95 
     96 	if (bus != 0)				/* XXX */
     97 		return NULL;
     98 
     99 	switch (device) {
    100 	case 6:					/* NCR SCSI */
    101 		pirq = 3;
    102 		break;
    103 
    104 	case 11:				/* slot 1 */
    105 		switch (pin) {
    106 		case PCI_INTERRUPT_PIN_A:
    107 		case PCI_INTERRUPT_PIN_D:
    108 			pirq = 0;
    109 			break;
    110 		case PCI_INTERRUPT_PIN_B:
    111 			pirq = 2;
    112 			break;
    113 		case PCI_INTERRUPT_PIN_C:
    114 			pirq = 1;
    115 			break;
    116 		};
    117 		break;
    118 
    119 	case 12:				/* slot 2 */
    120 		switch (pin) {
    121 		case PCI_INTERRUPT_PIN_A:
    122 		case PCI_INTERRUPT_PIN_D:
    123 			pirq = 1;
    124 			break;
    125 		case PCI_INTERRUPT_PIN_B:
    126 			pirq = 0;
    127 			break;
    128 		case PCI_INTERRUPT_PIN_C:
    129 			pirq = 2;
    130 			break;
    131 		};
    132 		break;
    133 
    134 	case 13:				/* slot 3 */
    135 		switch (pin) {
    136 		case PCI_INTERRUPT_PIN_A:
    137 		case PCI_INTERRUPT_PIN_D:
    138 			pirq = 2;
    139 			break;
    140 		case PCI_INTERRUPT_PIN_B:
    141 			pirq = 1;
    142 			break;
    143 		case PCI_INTERRUPT_PIN_C:
    144 			pirq = 0;
    145 			break;
    146 		};
    147 		break;
    148 	}
    149 
    150 	pirqreg = pci_conf_read(pci_make_tag(0, 7, 0), 0x60);	/* XXX */
    151 #if 0
    152 	printf("pci_2100_a50_map_int: device %d pin %c: pirq %d, reg = %x\n",
    153 		device, '@' + pin, pirq, pirqreg);
    154 #endif
    155 	line = (pirqreg >> (pirq * 8)) & 0xff;
    156 	if ((line & 0x80) != 0)
    157 		return 0;			/* not routed? */
    158 	line &= 0xf;
    159 
    160 #if 0
    161 	printf("pci_2100_a50_map_int: device %d pin %c: mapped to line %d\n",
    162 	    device, '@' + pin, line);
    163 #endif
    164 
    165 	return isa_intr_establish(line, ISA_IST_LEVEL, pcilevel_to_isa(level),
    166 	    func, arg);
    167 }
    168 
    169 void
    170 pci_2100_a50_pickintr()
    171 {
    172 	pcireg_t sioclass;
    173 	int sioII;
    174 
    175 	/* XXX MAGIC NUMBER */
    176 	sioclass = pci_conf_read(pci_make_tag(0, 7, 0), PCI_CLASS_REG);
    177         sioII = (sioclass & 0xff) >= 3;
    178 	if (!sioII)
    179 		printf("WARNING: SIO NOT SIO II... NO BETS...\n");
    180 
    181 	if (!sioII)
    182 		pci_cfg_fcns = &pci_2100_a50_sio1_cfg_fcns;
    183 	else
    184 		pci_cfg_fcns = &pci_2100_a50_sio2_cfg_fcns;
    185 
    186 	isa_intr_fcns = &sio_intr_fcns;
    187 	(*isa_intr_fcns->isa_intr_setup)();
    188 	set_iointr(isa_intr_fcns->isa_iointr);
    189 }
    190