pci_2100_a50.c revision 1.25.18.1
1 /* $NetBSD: pci_2100_a50.c,v 1.25.18.1 2000/06/22 16:58:40 minoura Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a50.c,v 1.25.18.1 2000/06/22 16:58:40 minoura Exp $"); 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/time.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <vm/vm.h> 41 42 #include <machine/autoconf.h> 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/isa/isavar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <alpha/pci/apecsvar.h> 51 52 #include <alpha/pci/pci_2100_a50.h> 53 #include <alpha/pci/siovar.h> 54 #include <alpha/pci/sioreg.h> 55 56 #include "sio.h" 57 58 int dec_2100_a50_intr_map __P((void *, pcitag_t, int, int, 59 pci_intr_handle_t *)); 60 const char *dec_2100_a50_intr_string __P((void *, pci_intr_handle_t)); 61 const struct evcnt *dec_2100_a50_intr_evcnt __P((void *, pci_intr_handle_t)); 62 void *dec_2100_a50_intr_establish __P((void *, pci_intr_handle_t, 63 int, int (*func)(void *), void *)); 64 void dec_2100_a50_intr_disestablish __P((void *, void *)); 65 66 #define APECS_SIO_DEVICE 7 /* XXX */ 67 68 void 69 pci_2100_a50_pickintr(acp) 70 struct apecs_config *acp; 71 { 72 bus_space_tag_t iot = &acp->ac_iot; 73 pci_chipset_tag_t pc = &acp->ac_pc; 74 pcireg_t sioclass; 75 int sioII; 76 77 /* XXX MAGIC NUMBER */ 78 sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG); 79 sioII = (sioclass & 0xff) >= 3; 80 81 if (!sioII) 82 printf("WARNING: SIO NOT SIO II... NO BETS...\n"); 83 84 pc->pc_intr_v = acp; 85 pc->pc_intr_map = dec_2100_a50_intr_map; 86 pc->pc_intr_string = dec_2100_a50_intr_string; 87 pc->pc_intr_evcnt = dec_2100_a50_intr_evcnt; 88 pc->pc_intr_establish = dec_2100_a50_intr_establish; 89 pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish; 90 91 /* Not supported on 2100 A50. */ 92 pc->pc_pciide_compat_intr_establish = NULL; 93 94 #if NSIO 95 sio_intr_setup(pc, iot); 96 set_iointr(&sio_iointr); 97 #else 98 panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)"); 99 #endif 100 } 101 102 int 103 dec_2100_a50_intr_map(acv, bustag, buspin, line, ihp) 104 void *acv; 105 pcitag_t bustag; 106 int buspin, line; 107 pci_intr_handle_t *ihp; 108 { 109 struct apecs_config *acp = acv; 110 pci_chipset_tag_t pc = &acp->ac_pc; 111 int device, pirq; 112 pcireg_t pirqreg; 113 u_int8_t pirqline; 114 115 #ifndef DIAGNOSTIC 116 pirq = 0; /* XXX gcc -Wuninitialized */ 117 #endif 118 119 if (buspin == 0) { 120 /* No IRQ used. */ 121 return 1; 122 } 123 if (buspin > 4) { 124 printf("dec_2100_a50_intr_map: bad interrupt pin %d\n", 125 buspin); 126 return 1; 127 } 128 129 alpha_pci_decompose_tag(pc, bustag, NULL, &device, NULL); 130 131 switch (device) { 132 case 6: /* NCR SCSI */ 133 pirq = 3; 134 break; 135 136 case 11: /* slot 1 */ 137 case 14: /* slot 3 */ 138 switch (buspin) { 139 case PCI_INTERRUPT_PIN_A: 140 case PCI_INTERRUPT_PIN_D: 141 pirq = 0; 142 break; 143 case PCI_INTERRUPT_PIN_B: 144 pirq = 2; 145 break; 146 case PCI_INTERRUPT_PIN_C: 147 pirq = 1; 148 break; 149 #ifdef DIAGNOSTIC 150 default: /* XXX gcc -Wuninitialized */ 151 panic("dec_2100_a50_intr_map bogus PCI pin %d\n", 152 buspin); 153 #endif 154 }; 155 break; 156 157 case 12: /* slot 2 */ 158 switch (buspin) { 159 case PCI_INTERRUPT_PIN_A: 160 case PCI_INTERRUPT_PIN_D: 161 pirq = 1; 162 break; 163 case PCI_INTERRUPT_PIN_B: 164 pirq = 0; 165 break; 166 case PCI_INTERRUPT_PIN_C: 167 pirq = 2; 168 break; 169 #ifdef DIAGNOSTIC 170 default: /* XXX gcc -Wuninitialized */ 171 panic("dec_2100_a50_intr_map bogus PCI pin %d\n", 172 buspin); 173 #endif 174 }; 175 break; 176 177 case 13: /* slot 3 */ 178 switch (buspin) { 179 case PCI_INTERRUPT_PIN_A: 180 case PCI_INTERRUPT_PIN_D: 181 pirq = 2; 182 break; 183 case PCI_INTERRUPT_PIN_B: 184 pirq = 1; 185 break; 186 case PCI_INTERRUPT_PIN_C: 187 pirq = 0; 188 break; 189 #ifdef DIAGNOSTIC 190 default: /* XXX gcc -Wuninitialized */ 191 panic("dec_2100_a50_intr_map bogus PCI pin %d\n", 192 buspin); 193 #endif 194 }; 195 break; 196 197 default: 198 printf("dec_2100_a50_intr_map: weird device number %d\n", 199 device); 200 return 1; 201 } 202 203 pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0), 204 SIO_PCIREG_PIRQ_RTCTRL); 205 #if 0 206 printf("pci_2100_a50_intr_map: device %d pin %c: pirq %d, reg = %x\n", 207 device, '@' + buspin, pirq, pirqreg); 208 #endif 209 pirqline = (pirqreg >> (pirq * 8)) & 0xff; 210 if ((pirqline & 0x80) != 0) 211 return 1; 212 pirqline &= 0xf; 213 214 #if 0 215 printf("pci_2100_a50_intr_map: device %d pin %c: mapped to line %d\n", 216 device, '@' + buspin, pirqline); 217 #endif 218 219 *ihp = pirqline; 220 return (0); 221 } 222 223 const char * 224 dec_2100_a50_intr_string(acv, ih) 225 void *acv; 226 pci_intr_handle_t ih; 227 { 228 #if 0 229 struct apecs_config *acp = acv; 230 #endif 231 232 return sio_intr_string(NULL /*XXX*/, ih); 233 } 234 235 const struct evcnt * 236 dec_2100_a50_intr_evcnt(acv, ih) 237 void *acv; 238 pci_intr_handle_t ih; 239 { 240 #if 0 241 struct apecs_config *acp = acv; 242 #endif 243 244 return sio_intr_evcnt(NULL /*XXX*/, ih); 245 } 246 247 void * 248 dec_2100_a50_intr_establish(acv, ih, level, func, arg) 249 void *acv, *arg; 250 pci_intr_handle_t ih; 251 int level; 252 int (*func) __P((void *)); 253 { 254 #if 0 255 struct apecs_config *acp = acv; 256 #endif 257 258 return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func, 259 arg); 260 } 261 262 void 263 dec_2100_a50_intr_disestablish(acv, cookie) 264 void *acv, *cookie; 265 { 266 #if 0 267 struct apecs_config *acp = acv; 268 #endif 269 270 sio_intr_disestablish(NULL /*XXX*/, cookie); 271 } 272
Indexes created Sun Oct 26 21:10:03 GMT 2025