pci_2100_a50.c revision 1.26
1 /* $NetBSD: pci_2100_a50.c,v 1.26 2000/06/04 19:14:21 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a50.c,v 1.26 2000/06/04 19:14:21 cgd Exp $"); 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/time.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <vm/vm.h> 41 42 #include <machine/autoconf.h> 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 #include <machine/intrcnt.h> 46 47 #include <dev/isa/isavar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 51 #include <alpha/pci/apecsvar.h> 52 53 #include <alpha/pci/pci_2100_a50.h> 54 #include <alpha/pci/siovar.h> 55 #include <alpha/pci/sioreg.h> 56 57 #include "sio.h" 58 59 int dec_2100_a50_intr_map __P((void *, pcitag_t, int, int, 60 pci_intr_handle_t *)); 61 const char *dec_2100_a50_intr_string __P((void *, pci_intr_handle_t)); 62 const struct evcnt *dec_2100_a50_intr_evcnt __P((void *, pci_intr_handle_t)); 63 void *dec_2100_a50_intr_establish __P((void *, pci_intr_handle_t, 64 int, int (*func)(void *), void *)); 65 void dec_2100_a50_intr_disestablish __P((void *, void *)); 66 67 #define APECS_SIO_DEVICE 7 /* XXX */ 68 69 void 70 pci_2100_a50_pickintr(acp) 71 struct apecs_config *acp; 72 { 73 bus_space_tag_t iot = &acp->ac_iot; 74 pci_chipset_tag_t pc = &acp->ac_pc; 75 pcireg_t sioclass; 76 int sioII; 77 78 /* XXX MAGIC NUMBER */ 79 sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG); 80 sioII = (sioclass & 0xff) >= 3; 81 82 if (!sioII) 83 printf("WARNING: SIO NOT SIO II... NO BETS...\n"); 84 85 pc->pc_intr_v = acp; 86 pc->pc_intr_map = dec_2100_a50_intr_map; 87 pc->pc_intr_string = dec_2100_a50_intr_string; 88 pc->pc_intr_evcnt = dec_2100_a50_intr_evcnt; 89 pc->pc_intr_establish = dec_2100_a50_intr_establish; 90 pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish; 91 92 /* Not supported on 2100 A50. */ 93 pc->pc_pciide_compat_intr_establish = NULL; 94 95 #if NSIO 96 sio_intr_setup(pc, iot); 97 set_iointr(&sio_iointr); 98 #else 99 panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)"); 100 #endif 101 } 102 103 int 104 dec_2100_a50_intr_map(acv, bustag, buspin, line, ihp) 105 void *acv; 106 pcitag_t bustag; 107 int buspin, line; 108 pci_intr_handle_t *ihp; 109 { 110 struct apecs_config *acp = acv; 111 pci_chipset_tag_t pc = &acp->ac_pc; 112 int device, pirq; 113 pcireg_t pirqreg; 114 u_int8_t pirqline; 115 116 #ifndef DIAGNOSTIC 117 pirq = 0; /* XXX gcc -Wuninitialized */ 118 #endif 119 120 if (buspin == 0) { 121 /* No IRQ used. */ 122 return 1; 123 } 124 if (buspin > 4) { 125 printf("dec_2100_a50_intr_map: bad interrupt pin %d\n", 126 buspin); 127 return 1; 128 } 129 130 alpha_pci_decompose_tag(pc, bustag, NULL, &device, NULL); 131 132 switch (device) { 133 case 6: /* NCR SCSI */ 134 pirq = 3; 135 break; 136 137 case 11: /* slot 1 */ 138 case 14: /* slot 3 */ 139 switch (buspin) { 140 case PCI_INTERRUPT_PIN_A: 141 case PCI_INTERRUPT_PIN_D: 142 pirq = 0; 143 break; 144 case PCI_INTERRUPT_PIN_B: 145 pirq = 2; 146 break; 147 case PCI_INTERRUPT_PIN_C: 148 pirq = 1; 149 break; 150 #ifdef DIAGNOSTIC 151 default: /* XXX gcc -Wuninitialized */ 152 panic("dec_2100_a50_intr_map bogus PCI pin %d\n", 153 buspin); 154 #endif 155 }; 156 break; 157 158 case 12: /* slot 2 */ 159 switch (buspin) { 160 case PCI_INTERRUPT_PIN_A: 161 case PCI_INTERRUPT_PIN_D: 162 pirq = 1; 163 break; 164 case PCI_INTERRUPT_PIN_B: 165 pirq = 0; 166 break; 167 case PCI_INTERRUPT_PIN_C: 168 pirq = 2; 169 break; 170 #ifdef DIAGNOSTIC 171 default: /* XXX gcc -Wuninitialized */ 172 panic("dec_2100_a50_intr_map bogus PCI pin %d\n", 173 buspin); 174 #endif 175 }; 176 break; 177 178 case 13: /* slot 3 */ 179 switch (buspin) { 180 case PCI_INTERRUPT_PIN_A: 181 case PCI_INTERRUPT_PIN_D: 182 pirq = 2; 183 break; 184 case PCI_INTERRUPT_PIN_B: 185 pirq = 1; 186 break; 187 case PCI_INTERRUPT_PIN_C: 188 pirq = 0; 189 break; 190 #ifdef DIAGNOSTIC 191 default: /* XXX gcc -Wuninitialized */ 192 panic("dec_2100_a50_intr_map bogus PCI pin %d\n", 193 buspin); 194 #endif 195 }; 196 break; 197 198 default: 199 printf("dec_2100_a50_intr_map: weird device number %d\n", 200 device); 201 return 1; 202 } 203 204 pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0), 205 SIO_PCIREG_PIRQ_RTCTRL); 206 #if 0 207 printf("pci_2100_a50_intr_map: device %d pin %c: pirq %d, reg = %x\n", 208 device, '@' + buspin, pirq, pirqreg); 209 #endif 210 pirqline = (pirqreg >> (pirq * 8)) & 0xff; 211 if ((pirqline & 0x80) != 0) 212 return 1; 213 pirqline &= 0xf; 214 215 #if 0 216 printf("pci_2100_a50_intr_map: device %d pin %c: mapped to line %d\n", 217 device, '@' + buspin, pirqline); 218 #endif 219 220 *ihp = pirqline; 221 return (0); 222 } 223 224 const char * 225 dec_2100_a50_intr_string(acv, ih) 226 void *acv; 227 pci_intr_handle_t ih; 228 { 229 #if 0 230 struct apecs_config *acp = acv; 231 #endif 232 233 return sio_intr_string(NULL /*XXX*/, ih); 234 } 235 236 const struct evcnt * 237 dec_2100_a50_intr_evcnt(acv, ih) 238 void *acv; 239 pci_intr_handle_t ih; 240 { 241 #if 0 242 struct apecs_config *acp = acv; 243 #endif 244 245 return sio_intr_evcnt(NULL /*XXX*/, ih); 246 } 247 248 void * 249 dec_2100_a50_intr_establish(acv, ih, level, func, arg) 250 void *acv, *arg; 251 pci_intr_handle_t ih; 252 int level; 253 int (*func) __P((void *)); 254 { 255 #if 0 256 struct apecs_config *acp = acv; 257 #endif 258 259 return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func, 260 arg); 261 } 262 263 void 264 dec_2100_a50_intr_disestablish(acv, cookie) 265 void *acv, *cookie; 266 { 267 #if 0 268 struct apecs_config *acp = acv; 269 #endif 270 271 sio_intr_disestablish(NULL /*XXX*/, cookie); 272 } 273
Indexes created Tue Sep 30 11:09:46 GMT 2025