pci_2100_a50.c revision 1.29
1 /* $NetBSD: pci_2100_a50.c,v 1.29 2000/12/28 22:59:07 sommerfeld Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a50.c,v 1.29 2000/12/28 22:59:07 sommerfeld Exp $"); 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/time.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <machine/autoconf.h> 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/isa/isavar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 51 #include <alpha/pci/apecsvar.h> 52 53 #include <alpha/pci/pci_2100_a50.h> 54 #include <alpha/pci/siovar.h> 55 #include <alpha/pci/sioreg.h> 56 57 #include "sio.h" 58 59 int dec_2100_a50_intr_map __P((struct pci_attach_args *, pci_intr_handle_t *)); 60 const char *dec_2100_a50_intr_string __P((void *, pci_intr_handle_t)); 61 const struct evcnt *dec_2100_a50_intr_evcnt __P((void *, pci_intr_handle_t)); 62 void *dec_2100_a50_intr_establish __P((void *, pci_intr_handle_t, 63 int, int (*func)(void *), void *)); 64 void dec_2100_a50_intr_disestablish __P((void *, void *)); 65 66 #define APECS_SIO_DEVICE 7 /* XXX */ 67 68 void 69 pci_2100_a50_pickintr(acp) 70 struct apecs_config *acp; 71 { 72 bus_space_tag_t iot = &acp->ac_iot; 73 pci_chipset_tag_t pc = &acp->ac_pc; 74 pcireg_t sioclass; 75 int sioII; 76 77 /* XXX MAGIC NUMBER */ 78 sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG); 79 sioII = (sioclass & 0xff) >= 3; 80 81 if (!sioII) 82 printf("WARNING: SIO NOT SIO II... NO BETS...\n"); 83 84 pc->pc_intr_v = acp; 85 pc->pc_intr_map = dec_2100_a50_intr_map; 86 pc->pc_intr_string = dec_2100_a50_intr_string; 87 pc->pc_intr_evcnt = dec_2100_a50_intr_evcnt; 88 pc->pc_intr_establish = dec_2100_a50_intr_establish; 89 pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish; 90 91 /* Not supported on 2100 A50. */ 92 pc->pc_pciide_compat_intr_establish = NULL; 93 94 #if NSIO 95 sio_intr_setup(pc, iot); 96 set_iointr(&sio_iointr); 97 #else 98 panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)"); 99 #endif 100 } 101 102 int 103 dec_2100_a50_intr_map(pa, ihp) 104 struct pci_attach_args *pa; 105 pci_intr_handle_t *ihp; 106 { 107 pcitag_t bustag = pa->pa_intrtag; 108 int buspin = pa->pa_intrpin; 109 pci_chipset_tag_t pc = pa->pa_pc; 110 int device, pirq; 111 pcireg_t pirqreg; 112 u_int8_t pirqline; 113 114 #ifndef DIAGNOSTIC 115 pirq = 0; /* XXX gcc -Wuninitialized */ 116 #endif 117 118 if (buspin == 0) { 119 /* No IRQ used. */ 120 return 1; 121 } 122 if (buspin > 4) { 123 printf("dec_2100_a50_intr_map: bad interrupt pin %d\n", 124 buspin); 125 return 1; 126 } 127 128 alpha_pci_decompose_tag(pc, bustag, NULL, &device, NULL); 129 130 switch (device) { 131 case 6: /* NCR SCSI */ 132 pirq = 3; 133 break; 134 135 case 11: /* slot 1 */ 136 case 14: /* slot 3 */ 137 switch (buspin) { 138 case PCI_INTERRUPT_PIN_A: 139 case PCI_INTERRUPT_PIN_D: 140 pirq = 0; 141 break; 142 case PCI_INTERRUPT_PIN_B: 143 pirq = 2; 144 break; 145 case PCI_INTERRUPT_PIN_C: 146 pirq = 1; 147 break; 148 #ifdef DIAGNOSTIC 149 default: /* XXX gcc -Wuninitialized */ 150 panic("dec_2100_a50_intr_map bogus PCI pin %d\n", 151 buspin); 152 #endif 153 }; 154 break; 155 156 case 12: /* slot 2 */ 157 switch (buspin) { 158 case PCI_INTERRUPT_PIN_A: 159 case PCI_INTERRUPT_PIN_D: 160 pirq = 1; 161 break; 162 case PCI_INTERRUPT_PIN_B: 163 pirq = 0; 164 break; 165 case PCI_INTERRUPT_PIN_C: 166 pirq = 2; 167 break; 168 #ifdef DIAGNOSTIC 169 default: /* XXX gcc -Wuninitialized */ 170 panic("dec_2100_a50_intr_map bogus PCI pin %d\n", 171 buspin); 172 #endif 173 }; 174 break; 175 176 case 13: /* slot 3 */ 177 switch (buspin) { 178 case PCI_INTERRUPT_PIN_A: 179 case PCI_INTERRUPT_PIN_D: 180 pirq = 2; 181 break; 182 case PCI_INTERRUPT_PIN_B: 183 pirq = 1; 184 break; 185 case PCI_INTERRUPT_PIN_C: 186 pirq = 0; 187 break; 188 #ifdef DIAGNOSTIC 189 default: /* XXX gcc -Wuninitialized */ 190 panic("dec_2100_a50_intr_map bogus PCI pin %d\n", 191 buspin); 192 #endif 193 }; 194 break; 195 196 default: 197 printf("dec_2100_a50_intr_map: weird device number %d\n", 198 device); 199 return 1; 200 } 201 202 pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0), 203 SIO_PCIREG_PIRQ_RTCTRL); 204 #if 0 205 printf("pci_2100_a50_intr_map: device %d pin %c: pirq %d, reg = %x\n", 206 device, '@' + buspin, pirq, pirqreg); 207 #endif 208 pirqline = (pirqreg >> (pirq * 8)) & 0xff; 209 if ((pirqline & 0x80) != 0) 210 return 1; 211 pirqline &= 0xf; 212 213 #if 0 214 printf("pci_2100_a50_intr_map: device %d pin %c: mapped to line %d\n", 215 device, '@' + buspin, pirqline); 216 #endif 217 218 *ihp = pirqline; 219 return (0); 220 } 221 222 const char * 223 dec_2100_a50_intr_string(acv, ih) 224 void *acv; 225 pci_intr_handle_t ih; 226 { 227 #if 0 228 struct apecs_config *acp = acv; 229 #endif 230 231 return sio_intr_string(NULL /*XXX*/, ih); 232 } 233 234 const struct evcnt * 235 dec_2100_a50_intr_evcnt(acv, ih) 236 void *acv; 237 pci_intr_handle_t ih; 238 { 239 #if 0 240 struct apecs_config *acp = acv; 241 #endif 242 243 return sio_intr_evcnt(NULL /*XXX*/, ih); 244 } 245 246 void * 247 dec_2100_a50_intr_establish(acv, ih, level, func, arg) 248 void *acv, *arg; 249 pci_intr_handle_t ih; 250 int level; 251 int (*func) __P((void *)); 252 { 253 #if 0 254 struct apecs_config *acp = acv; 255 #endif 256 257 return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func, 258 arg); 259 } 260 261 void 262 dec_2100_a50_intr_disestablish(acv, cookie) 263 void *acv, *cookie; 264 { 265 #if 0 266 struct apecs_config *acp = acv; 267 #endif 268 269 sio_intr_disestablish(NULL /*XXX*/, cookie); 270 } 271
Indexes created Tue Sep 30 11:09:46 GMT 2025