pci_2100_a50.c revision 1.43
1 /* $NetBSD: pci_2100_a50.c,v 1.43 2021/06/19 16:59:07 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a50.c,v 1.43 2021/06/19 16:59:07 thorpej Exp $"); 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/time.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 41 #include <machine/autoconf.h> 42 #include <machine/rpb.h> 43 #include <sys/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/isa/isavar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <alpha/pci/apecsvar.h> 51 52 #include <alpha/pci/siovar.h> 53 #include <alpha/pci/sioreg.h> 54 55 #include "sio.h" 56 57 static int dec_2100_a50_intr_map(const struct pci_attach_args *, 58 pci_intr_handle_t *); 59 60 #define APECS_SIO_DEVICE 7 /* XXX */ 61 62 static void 63 pci_2100_a50_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, 64 pci_chipset_tag_t pc) 65 { 66 pcireg_t sioclass; 67 int sioII; 68 69 /* XXX MAGIC NUMBER */ 70 sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG); 71 sioII = (sioclass & 0xff) >= 3; 72 73 if (!sioII) 74 printf("WARNING: SIO NOT SIO II... NO BETS...\n"); 75 76 pc->pc_intr_v = core; 77 pc->pc_intr_map = dec_2100_a50_intr_map; 78 pc->pc_intr_string = sio_pci_intr_string; 79 pc->pc_intr_evcnt = sio_pci_intr_evcnt; 80 pc->pc_intr_establish = sio_pci_intr_establish; 81 pc->pc_intr_disestablish = sio_pci_intr_disestablish; 82 83 /* Not supported on 2100 A50. */ 84 pc->pc_pciide_compat_intr_establish = NULL; 85 86 #if NSIO 87 sio_intr_setup(pc, iot); 88 #else 89 panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)"); 90 #endif 91 } 92 ALPHA_PCI_INTR_INIT(ST_DEC_2100_A50, pci_2100_a50_pickintr) 93 94 int 95 dec_2100_a50_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 96 { 97 pcitag_t bustag = pa->pa_intrtag; 98 int buspin = pa->pa_intrpin; 99 pci_chipset_tag_t pc = pa->pa_pc; 100 int device, pirq; 101 pcireg_t pirqreg; 102 uint8_t pirqline; 103 104 #ifndef DIAGNOSTIC 105 pirq = 0; /* XXX gcc -Wuninitialized */ 106 #endif 107 108 if (buspin == 0) { 109 /* No IRQ used. */ 110 return 1; 111 } 112 if (buspin < 0 || buspin > 4) { 113 printf("dec_2100_a50_intr_map: bad interrupt pin %d\n", 114 buspin); 115 return 1; 116 } 117 118 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 119 120 switch (device) { 121 case 6: /* NCR SCSI */ 122 pirq = 3; 123 break; 124 125 case 11: /* slot 1 */ 126 case 14: /* slot 3 */ 127 switch (buspin) { 128 case PCI_INTERRUPT_PIN_A: 129 case PCI_INTERRUPT_PIN_D: 130 pirq = 0; 131 break; 132 case PCI_INTERRUPT_PIN_B: 133 pirq = 2; 134 break; 135 case PCI_INTERRUPT_PIN_C: 136 pirq = 1; 137 break; 138 #ifdef DIAGNOSTIC 139 default: /* XXX gcc -Wuninitialized */ 140 panic("dec_2100_a50_intr_map bogus PCI pin %d", 141 buspin); 142 #endif 143 }; 144 break; 145 146 case 12: /* slot 2 */ 147 switch (buspin) { 148 case PCI_INTERRUPT_PIN_A: 149 case PCI_INTERRUPT_PIN_D: 150 pirq = 1; 151 break; 152 case PCI_INTERRUPT_PIN_B: 153 pirq = 0; 154 break; 155 case PCI_INTERRUPT_PIN_C: 156 pirq = 2; 157 break; 158 #ifdef DIAGNOSTIC 159 default: /* XXX gcc -Wuninitialized */ 160 panic("dec_2100_a50_intr_map bogus PCI pin %d", 161 buspin); 162 #endif 163 }; 164 break; 165 166 case 13: /* slot 3 */ 167 switch (buspin) { 168 case PCI_INTERRUPT_PIN_A: 169 case PCI_INTERRUPT_PIN_D: 170 pirq = 2; 171 break; 172 case PCI_INTERRUPT_PIN_B: 173 pirq = 1; 174 break; 175 case PCI_INTERRUPT_PIN_C: 176 pirq = 0; 177 break; 178 #ifdef DIAGNOSTIC 179 default: /* XXX gcc -Wuninitialized */ 180 panic("dec_2100_a50_intr_map bogus PCI pin %d", 181 buspin); 182 #endif 183 }; 184 break; 185 186 default: 187 printf("dec_2100_a50_intr_map: weird device number %d\n", 188 device); 189 return 1; 190 } 191 192 pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0), 193 SIO_PCIREG_PIRQ_RTCTRL); 194 #if 0 195 printf("pci_2100_a50_intr_map: device %d pin %c: pirq %d, reg = %x\n", 196 device, '@' + buspin, pirq, pirqreg); 197 #endif 198 pirqline = (pirqreg >> (pirq * 8)) & 0xff; 199 if ((pirqline & 0x80) != 0) 200 return 1; 201 pirqline &= 0xf; 202 203 #if 0 204 printf("pci_2100_a50_intr_map: device %d pin %c: mapped to line %d\n", 205 device, '@' + buspin, pirqline); 206 #endif 207 208 alpha_pci_intr_handle_init(ihp, pirqline, 0); 209 return (0); 210 } 211
Indexes created Tue Sep 30 20:09:53 GMT 2025