pci_2100_a50.c revision 1.8
1 /* $NetBSD: pci_2100_a50.c,v 1.8 1996/07/14 04:08:21 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/types.h> 31 #include <sys/param.h> 32 #include <sys/time.h> 33 #include <sys/systm.h> 34 #include <sys/errno.h> 35 #include <sys/device.h> 36 #include <vm/vm.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/isa/isavar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 #include <alpha/pci/apecsvar.h> 47 48 #include <alpha/pci/pci_2100_a50.h> 49 #include <alpha/pci/siovar.h> 50 #include <alpha/pci/sioreg.h> 51 52 #include "sio.h" 53 54 int dec_2100_a50_intr_map __P((void *, pcitag_t, int, int, 55 pci_intr_handle_t *)); 56 const char *dec_2100_a50_intr_string __P((void *, pci_intr_handle_t)); 57 void *dec_2100_a50_intr_establish __P((void *, pci_intr_handle_t, 58 int, int (*func)(void *), void *)); 59 void dec_2100_a50_intr_disestablish __P((void *, void *)); 60 61 #define APECS_SIO_DEVICE 7 /* XXX */ 62 63 void 64 pci_2100_a50_pickintr(acp) 65 struct apecs_config *acp; 66 { 67 bus_chipset_tag_t bc = &acp->ac_bc; 68 pci_chipset_tag_t pc = &acp->ac_pc; 69 pcireg_t sioclass; 70 int sioII; 71 72 /* XXX MAGIC NUMBER */ 73 sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG); 74 sioII = (sioclass & 0xff) >= 3; 75 76 if (!sioII) 77 printf("WARNING: SIO NOT SIO II... NO BETS...\n"); 78 79 pc->pc_intr_v = acp; 80 pc->pc_intr_map = dec_2100_a50_intr_map; 81 pc->pc_intr_string = dec_2100_a50_intr_string; 82 pc->pc_intr_establish = dec_2100_a50_intr_establish; 83 pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish; 84 85 #if NSIO 86 sio_intr_setup(bc); 87 set_iointr(&sio_iointr); 88 #else 89 panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)"); 90 #endif 91 } 92 93 int 94 dec_2100_a50_intr_map(acv, bustag, buspin, line, ihp) 95 void *acv; 96 pcitag_t bustag; 97 int buspin, line; 98 pci_intr_handle_t *ihp; 99 { 100 struct apecs_config *acp = acv; 101 pci_chipset_tag_t pc = &acp->ac_pc; 102 int device, pirq; 103 pcireg_t pirqreg; 104 u_int8_t pirqline; 105 106 if (buspin == 0) { 107 /* No IRQ used. */ 108 return 1; 109 } 110 if (buspin > 4) { 111 printf("pci_map_int: bad interrupt pin %d\n", buspin); 112 return 1; 113 } 114 115 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 116 117 switch (device) { 118 case 6: /* NCR SCSI */ 119 pirq = 3; 120 break; 121 122 case 11: /* slot 1 */ 123 case 14: /* slot 3 */ 124 switch (buspin) { 125 case PCI_INTERRUPT_PIN_A: 126 case PCI_INTERRUPT_PIN_D: 127 pirq = 0; 128 break; 129 case PCI_INTERRUPT_PIN_B: 130 pirq = 2; 131 break; 132 case PCI_INTERRUPT_PIN_C: 133 pirq = 1; 134 break; 135 }; 136 break; 137 138 case 12: /* slot 2 */ 139 switch (buspin) { 140 case PCI_INTERRUPT_PIN_A: 141 case PCI_INTERRUPT_PIN_D: 142 pirq = 1; 143 break; 144 case PCI_INTERRUPT_PIN_B: 145 pirq = 0; 146 break; 147 case PCI_INTERRUPT_PIN_C: 148 pirq = 2; 149 break; 150 }; 151 break; 152 153 case 13: /* slot 3 */ 154 switch (buspin) { 155 case PCI_INTERRUPT_PIN_A: 156 case PCI_INTERRUPT_PIN_D: 157 pirq = 2; 158 break; 159 case PCI_INTERRUPT_PIN_B: 160 pirq = 1; 161 break; 162 case PCI_INTERRUPT_PIN_C: 163 pirq = 0; 164 break; 165 }; 166 break; 167 } 168 169 pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0), 170 SIO_PCIREG_PIRQ_RTCTRL); 171 #if 0 172 printf("pci_2100_a50_map_int: device %d pin %c: pirq %d, reg = %x\n", 173 device, '@' + buspin, pirq, pirqreg); 174 #endif 175 pirqline = (pirqreg >> (pirq * 8)) & 0xff; 176 if ((pirqline & 0x80) != 0) 177 return 1; 178 pirqline &= 0xf; 179 180 #if 0 181 printf("pci_2100_a50_map_int: device %d pin %c: mapped to line %d\n", 182 device, '@' + buspin, pirqline); 183 #endif 184 185 *ihp = pirqline; 186 return (0); 187 } 188 189 const char * 190 dec_2100_a50_intr_string(acv, ih) 191 void *acv; 192 pci_intr_handle_t ih; 193 { 194 struct apecs_config *acp = acv; 195 196 return sio_intr_string(NULL /*XXX*/, ih); 197 } 198 199 void * 200 dec_2100_a50_intr_establish(acv, ih, level, func, arg) 201 void *acv, *arg; 202 pci_intr_handle_t ih; 203 int level; 204 int (*func) __P((void *)); 205 { 206 struct apecs_config *acp = acv; 207 208 return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func, 209 arg); 210 } 211 212 void 213 dec_2100_a50_intr_disestablish(acv, cookie) 214 void *acv, *cookie; 215 { 216 struct apecs_config *acp = acv; 217 218 sio_intr_disestablish(NULL /*XXX*/, cookie); 219 } 220
Indexes created Tue Sep 30 11:09:46 GMT 2025