pci_6600.c revision 1.1 1 1.1 ross /* $NetBSD: pci_6600.c,v 1.1 1999/06/29 06:46:46 ross Exp $ */
2 1.1 ross
3 1.1 ross /*-
4 1.1 ross * Copyright (c) 1999 by Ross Harvey. All rights reserved.
5 1.1 ross *
6 1.1 ross * Redistribution and use in source and binary forms, with or without
7 1.1 ross * modification, are permitted provided that the following conditions
8 1.1 ross * are met:
9 1.1 ross * 1. Redistributions of source code must retain the above copyright
10 1.1 ross * notice, this list of conditions and the following disclaimer.
11 1.1 ross * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 ross * notice, this list of conditions and the following disclaimer in the
13 1.1 ross * documentation and/or other materials provided with the distribution.
14 1.1 ross * 3. All advertising materials mentioning features or use of this software
15 1.1 ross * must display the following acknowledgement:
16 1.1 ross * This product includes software developed by Ross Harvey.
17 1.1 ross * 4. The name of Ross Harvey may not be used to endorse or promote products
18 1.1 ross * derived from this software without specific prior written permission.
19 1.1 ross *
20 1.1 ross * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
21 1.1 ross * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 1.1 ross * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
23 1.1 ross * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
24 1.1 ross * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 1.1 ross * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 1.1 ross * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 1.1 ross * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 1.1 ross * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 1.1 ross * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 1.1 ross * SUCH DAMAGE.
31 1.1 ross *
32 1.1 ross */
33 1.1 ross
34 1.1 ross #include <sys/cdefs.h>
35 1.1 ross
36 1.1 ross __KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.1 1999/06/29 06:46:46 ross Exp $");
37 1.1 ross
38 1.1 ross #include <sys/param.h>
39 1.1 ross #include <sys/systm.h>
40 1.1 ross #include <sys/kernel.h>
41 1.1 ross #include <sys/device.h>
42 1.1 ross #include <sys/malloc.h>
43 1.1 ross #include <vm/vm.h>
44 1.1 ross
45 1.1 ross #include <machine/autoconf.h>
46 1.1 ross #define _ALPHA_BUS_DMA_PRIVATE
47 1.1 ross #include <machine/bus.h>
48 1.1 ross #include <machine/rpb.h>
49 1.1 ross #include <machine/intrcnt.h>
50 1.1 ross #include <machine/alpha.h>
51 1.1 ross
52 1.1 ross #include <dev/pci/pcireg.h>
53 1.1 ross #include <dev/pci/pcivar.h>
54 1.1 ross #include <dev/pci/pciidereg.h>
55 1.1 ross #include <dev/pci/pciidevar.h>
56 1.1 ross
57 1.1 ross #include <alpha/pci/tsreg.h>
58 1.1 ross #include <alpha/pci/tsvar.h>
59 1.1 ross #include <alpha/pci/pci_6600.h>
60 1.1 ross
61 1.1 ross #define pci_6600() { Generate ctags(1) key. }
62 1.1 ross
63 1.1 ross #include "sio.h"
64 1.1 ross #if NSIO
65 1.1 ross #include <alpha/pci/siovar.h>
66 1.1 ross #endif
67 1.1 ross
68 1.1 ross #define PCI_STRAY_MAX 5
69 1.1 ross #define DEC_6600_MAX_IRQ INTRCNT_OTHER_LEN
70 1.1 ross
71 1.1 ross static char *irqtype = "6600 irq";
72 1.1 ross static struct tsp_config *sioprimary;
73 1.1 ross
74 1.1 ross static void checkmaxirq __P((pci_intr_handle_t ih));
75 1.1 ross void dec_6600_intr_disestablish __P((void *, void *));
76 1.1 ross void *dec_6600_intr_establish __P((
77 1.1 ross void *, pci_intr_handle_t, int, int (*func)(void *), void *));
78 1.1 ross const char *dec_6600_intr_string __P((void *, pci_intr_handle_t));
79 1.1 ross int dec_6600_intr_map __P((void *, pcitag_t, int, int, pci_intr_handle_t *));
80 1.1 ross void *dec_6600_pciide_compat_intr_establish __P((void *, struct device *,
81 1.1 ross struct pci_attach_args *, int, int (*)(void *), void *));
82 1.1 ross
83 1.1 ross struct alpha_shared_intr *dec_6600_pci_intr;
84 1.1 ross
85 1.1 ross void dec_6600_iointr __P((void *framep, unsigned long vec));
86 1.1 ross extern void dec_6600_intr_enable __P((int irq));
87 1.1 ross extern void dec_6600_intr_disable __P((int irq));
88 1.1 ross
89 1.1 ross void
90 1.1 ross pci_6600_pickintr(pcp)
91 1.1 ross struct tsp_config *pcp;
92 1.1 ross {
93 1.1 ross bus_space_tag_t iot = &pcp->pc_iot;
94 1.1 ross pci_chipset_tag_t pc = &pcp->pc_pc;
95 1.1 ross int i;
96 1.1 ross
97 1.1 ross pc->pc_intr_v = pcp;
98 1.1 ross pc->pc_intr_map = dec_6600_intr_map;
99 1.1 ross pc->pc_intr_string = dec_6600_intr_string;
100 1.1 ross pc->pc_intr_establish = dec_6600_intr_establish;
101 1.1 ross pc->pc_intr_disestablish = dec_6600_intr_disestablish;
102 1.1 ross pc->pc_pciide_compat_intr_establish = NULL;
103 1.1 ross
104 1.1 ross /*
105 1.1 ross * System-wide and Pchip-0-only logic...
106 1.1 ross */
107 1.1 ross if (dec_6600_pci_intr == NULL) {
108 1.1 ross sioprimary = pcp;
109 1.1 ross pc->pc_pciide_compat_intr_establish =
110 1.1 ross dec_6600_pciide_compat_intr_establish;
111 1.1 ross dec_6600_pci_intr = alpha_shared_intr_alloc(DEC_6600_MAX_IRQ);
112 1.1 ross for (i = 0; i < DEC_6600_MAX_IRQ; i++)
113 1.1 ross alpha_shared_intr_set_maxstrays(dec_6600_pci_intr, i,
114 1.1 ross PCI_STRAY_MAX);
115 1.1 ross #if NSIO
116 1.1 ross sio_intr_setup(pc, iot);
117 1.1 ross dec_6600_intr_enable(55); /* irq line for sio */
118 1.1 ross #endif
119 1.1 ross set_iointr(dec_6600_iointr);
120 1.1 ross }
121 1.1 ross }
122 1.1 ross
123 1.1 ross int
124 1.1 ross dec_6600_intr_map(acv, bustag, buspin, line, ihp)
125 1.1 ross void *acv;
126 1.1 ross pcitag_t bustag;
127 1.1 ross int buspin, line;
128 1.1 ross pci_intr_handle_t *ihp;
129 1.1 ross {
130 1.1 ross struct tsp_config *pcp = acv;
131 1.1 ross pci_chipset_tag_t pc = &pcp->pc_pc;
132 1.1 ross int bus, device, function;
133 1.1 ross
134 1.1 ross if (buspin == 0) {
135 1.1 ross /* No IRQ used. */
136 1.1 ross return 1;
137 1.1 ross }
138 1.1 ross if (buspin > 4) {
139 1.1 ross printf("intr_map: bad interrupt pin %d\n", buspin);
140 1.1 ross return 1;
141 1.1 ross }
142 1.1 ross
143 1.1 ross /*
144 1.1 ross * The console places the interrupt mapping in the "line" value.
145 1.1 ross * A value of (char)-1 indicates there is no mapping.
146 1.1 ross */
147 1.1 ross if (line >= 64) { /* for usb host bridge, line == 0xea (?!) */
148 1.1 ross alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function);
149 1.1 ross printf("intr_map: line=0x%x, no mapping for %d/%d/%d\n",
150 1.1 ross line, bus, device, function);
151 1.1 ross return (1);
152 1.1 ross }
153 1.1 ross
154 1.1 ross if (line >= INTRCNT_OTHER_LEN)
155 1.1 ross panic("intr_map: irq too large (%d)\n", line);
156 1.1 ross
157 1.1 ross *ihp = line;
158 1.1 ross checkmaxirq(*ihp);
159 1.1 ross return (0);
160 1.1 ross }
161 1.1 ross
162 1.1 ross static void
163 1.1 ross checkmaxirq(ih)
164 1.1 ross pci_intr_handle_t ih;
165 1.1 ross {
166 1.1 ross if (ih > DEC_6600_MAX_IRQ)
167 1.1 ross panic("extreme irq %ld\n", ih);
168 1.1 ross }
169 1.1 ross
170 1.1 ross const char *
171 1.1 ross dec_6600_intr_string(acv, ih)
172 1.1 ross void *acv;
173 1.1 ross pci_intr_handle_t ih;
174 1.1 ross {
175 1.1 ross
176 1.1 ross static const char irqfmt[] = "dec_6600 irq %ld";
177 1.1 ross static char irqstr[sizeof irqfmt];
178 1.1 ross
179 1.1 ross checkmaxirq(ih);
180 1.1 ross snprintf(irqstr, sizeof irqstr, irqfmt, ih);
181 1.1 ross return (irqstr);
182 1.1 ross }
183 1.1 ross
184 1.1 ross void *
185 1.1 ross dec_6600_intr_establish(acv, ih, level, func, arg)
186 1.1 ross void *acv, *arg;
187 1.1 ross pci_intr_handle_t ih;
188 1.1 ross int level;
189 1.1 ross int (*func) __P((void *));
190 1.1 ross {
191 1.1 ross void *cookie;
192 1.1 ross
193 1.1 ross checkmaxirq(ih);
194 1.1 ross cookie = alpha_shared_intr_establish(dec_6600_pci_intr, ih, IST_LEVEL,
195 1.1 ross level, func, arg, irqtype);
196 1.1 ross
197 1.1 ross if (cookie != NULL && alpha_shared_intr_isactive(dec_6600_pci_intr, ih))
198 1.1 ross dec_6600_intr_enable(ih);
199 1.1 ross return (cookie);
200 1.1 ross }
201 1.1 ross
202 1.1 ross void
203 1.1 ross dec_6600_intr_disestablish(acv, cookie)
204 1.1 ross void *acv, *cookie;
205 1.1 ross {
206 1.1 ross struct alpha_shared_intrhand *ih = cookie;
207 1.1 ross unsigned int irq = ih->ih_num;
208 1.1 ross int s;
209 1.1 ross
210 1.1 ross s = splhigh();
211 1.1 ross
212 1.1 ross alpha_shared_intr_disestablish(dec_6600_pci_intr, cookie, irqtype);
213 1.1 ross if (alpha_shared_intr_isactive(dec_6600_pci_intr, irq) == 0) {
214 1.1 ross dec_6600_intr_disable(irq);
215 1.1 ross alpha_shared_intr_set_dfltsharetype(dec_6600_pci_intr, irq,
216 1.1 ross IST_NONE);
217 1.1 ross }
218 1.1 ross
219 1.1 ross splx(s);
220 1.1 ross }
221 1.1 ross
222 1.1 ross void
223 1.1 ross dec_6600_iointr(framep, vec)
224 1.1 ross void *framep;
225 1.1 ross unsigned long vec;
226 1.1 ross {
227 1.1 ross int irq;
228 1.1 ross
229 1.1 ross if (vec >= 0x900) {
230 1.1 ross irq = (vec - 0x900) >> 4;
231 1.1 ross
232 1.1 ross if(irq >= INTRCNT_OTHER_LEN)
233 1.1 ross panic("iointr: irq %d is too high", irq);
234 1.1 ross ++intrcnt[INTRCNT_OTHER_BASE + irq];
235 1.1 ross
236 1.1 ross if (!alpha_shared_intr_dispatch(dec_6600_pci_intr, irq)) {
237 1.1 ross alpha_shared_intr_stray(dec_6600_pci_intr, irq,
238 1.1 ross irqtype);
239 1.1 ross if (ALPHA_SHARED_INTR_DISABLE(dec_6600_pci_intr, irq))
240 1.1 ross dec_6600_intr_disable(irq);
241 1.1 ross }
242 1.1 ross return;
243 1.1 ross }
244 1.1 ross #if NSIO
245 1.1 ross if (vec >= 0x800) {
246 1.1 ross sio_iointr(framep, vec);
247 1.1 ross return;
248 1.1 ross }
249 1.1 ross #endif
250 1.1 ross panic("iointr: weird vec 0x%lx\n", vec);
251 1.1 ross }
252 1.1 ross
253 1.1 ross void
254 1.1 ross dec_6600_intr_enable(irq)
255 1.1 ross int irq;
256 1.1 ross {
257 1.1 ross alpha_mb();
258 1.1 ross STQP(TS_C_DIM0) |= 1UL << irq;
259 1.1 ross alpha_mb();
260 1.1 ross }
261 1.1 ross
262 1.1 ross void
263 1.1 ross dec_6600_intr_disable(irq)
264 1.1 ross int irq;
265 1.1 ross {
266 1.1 ross alpha_mb();
267 1.1 ross STQP(TS_C_DIM0) &= ~(1UL << irq);
268 1.1 ross alpha_mb();
269 1.1 ross }
270 1.1 ross
271 1.1 ross void *
272 1.1 ross dec_6600_pciide_compat_intr_establish(v, dev, pa, chan, func, arg)
273 1.1 ross void *v;
274 1.1 ross struct device *dev;
275 1.1 ross struct pci_attach_args *pa;
276 1.1 ross int chan;
277 1.1 ross int (*func) __P((void *));
278 1.1 ross void *arg;
279 1.1 ross {
280 1.1 ross pci_chipset_tag_t pc = pa->pa_pc;
281 1.1 ross void *cookie = NULL;
282 1.1 ross int bus, irq;
283 1.1 ross
284 1.1 ross alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
285 1.1 ross
286 1.1 ross if (bus != 0 || pc->pc_intr_v != sioprimary)
287 1.1 ross printf("Warning: strange pciide\n");
288 1.1 ross
289 1.1 ross irq = PCIIDE_COMPAT_IRQ(chan);
290 1.1 ross #if NSIO
291 1.1 ross cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO,
292 1.1 ross func, arg);
293 1.1 ross #endif
294 1.1 ross return (cookie);
295 1.1 ross }
296