pci_6600.c revision 1.20.2.1
1 /* $NetBSD: pci_6600.c,v 1.20.2.1 2011/06/06 09:04:45 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.20.2.1 2011/06/06 09:04:45 jruoho Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <machine/autoconf.h> 45 #define _ALPHA_BUS_DMA_PRIVATE 46 #include <machine/bus.h> 47 #include <machine/rpb.h> 48 #include <machine/alpha.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pciidereg.h> 53 #include <dev/pci/pciidevar.h> 54 55 #include <alpha/pci/tsreg.h> 56 #include <alpha/pci/tsvar.h> 57 #include <alpha/pci/pci_6600.h> 58 59 #define pci_6600() { Generate ctags(1) key. } 60 61 #include "sio.h" 62 #if NSIO 63 #include <alpha/pci/siovar.h> 64 #endif 65 66 #define PCI_NIRQ 64 67 #define PCI_STRAY_MAX 5 68 69 /* 70 * Some Tsunami models have a PCI device (the USB controller) with interrupts 71 * tied to ISA IRQ lines. The IRQ is encoded as: 72 * 73 * line = 0xe0 | isa_irq; 74 */ 75 #define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef) 76 #define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f) 77 78 static const char *irqtype = "6600 irq"; 79 static struct tsp_config *sioprimary; 80 81 void dec_6600_intr_disestablish(void *, void *); 82 void *dec_6600_intr_establish( 83 void *, pci_intr_handle_t, int, int (*func)(void *), void *); 84 const char *dec_6600_intr_string(void *, pci_intr_handle_t); 85 const struct evcnt *dec_6600_intr_evcnt(void *, pci_intr_handle_t); 86 int dec_6600_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 87 void *dec_6600_pciide_compat_intr_establish(void *, struct device *, 88 const struct pci_attach_args *, int, int (*)(void *), void *); 89 90 struct alpha_shared_intr *dec_6600_pci_intr; 91 92 void dec_6600_iointr(void *arg, unsigned long vec); 93 extern void dec_6600_intr_enable(int irq); 94 extern void dec_6600_intr_disable(int irq); 95 96 void 97 pci_6600_pickintr(struct tsp_config *pcp) 98 { 99 bus_space_tag_t iot = &pcp->pc_iot; 100 pci_chipset_tag_t pc = &pcp->pc_pc; 101 char *cp; 102 int i; 103 104 pc->pc_intr_v = pcp; 105 pc->pc_intr_map = dec_6600_intr_map; 106 pc->pc_intr_string = dec_6600_intr_string; 107 pc->pc_intr_evcnt = dec_6600_intr_evcnt; 108 pc->pc_intr_establish = dec_6600_intr_establish; 109 pc->pc_intr_disestablish = dec_6600_intr_disestablish; 110 pc->pc_pciide_compat_intr_establish = NULL; 111 112 /* 113 * System-wide and Pchip-0-only logic... 114 */ 115 if (dec_6600_pci_intr == NULL) { 116 sioprimary = pcp; 117 pc->pc_pciide_compat_intr_establish = 118 dec_6600_pciide_compat_intr_establish; 119 dec_6600_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ, 8); 120 for (i = 0; i < PCI_NIRQ; i++) { 121 alpha_shared_intr_set_maxstrays(dec_6600_pci_intr, i, 122 PCI_STRAY_MAX); 123 alpha_shared_intr_set_private(dec_6600_pci_intr, i, 124 sioprimary); 125 126 cp = alpha_shared_intr_string(dec_6600_pci_intr, i); 127 sprintf(cp, "irq %d", i); 128 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 129 dec_6600_pci_intr, i), EVCNT_TYPE_INTR, NULL, 130 "dec_6600", cp); 131 } 132 #if NSIO 133 sio_intr_setup(pc, iot); 134 dec_6600_intr_enable(55); /* irq line for sio */ 135 #endif 136 } 137 } 138 139 int 140 dec_6600_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 141 { 142 pcitag_t bustag = pa->pa_intrtag; 143 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 144 pci_chipset_tag_t pc = pa->pa_pc; 145 int bus, device, function; 146 147 if (buspin == 0) { 148 /* No IRQ used. */ 149 return 1; 150 } 151 if (buspin > 4) { 152 printf("intr_map: bad interrupt pin %d\n", buspin); 153 return 1; 154 } 155 156 pci_decompose_tag(pc, bustag, &bus, &device, &function); 157 158 /* 159 * The console places the interrupt mapping in the "line" value. 160 * A value of (char)-1 indicates there is no mapping. 161 */ 162 if (line == 0xff) { 163 printf("dec_6600_intr_map: no mapping for %d/%d/%d\n", 164 bus, device, function); 165 return (1); 166 } 167 168 #if NSIO == 0 169 if (DEC_6600_LINE_IS_ISA(line)) { 170 printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n", 171 DEC_6600_LINE_ISA_IRQ(line), bus, device, function); 172 return (1); 173 } 174 #endif 175 176 if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= PCI_NIRQ) 177 panic("dec_6600_intr_map: dec 6600 irq too large (%d)", 178 line); 179 180 *ihp = line; 181 return (0); 182 } 183 184 const char * 185 dec_6600_intr_string(void *acv, pci_intr_handle_t ih) 186 { 187 188 static const char irqfmt[] = "dec 6600 irq %ld"; 189 static char irqstr[sizeof irqfmt]; 190 191 #if NSIO 192 if (DEC_6600_LINE_IS_ISA(ih)) 193 return (sio_intr_string(NULL /*XXX*/, 194 DEC_6600_LINE_ISA_IRQ(ih))); 195 #endif 196 197 snprintf(irqstr, sizeof irqstr, irqfmt, ih); 198 return (irqstr); 199 } 200 201 const struct evcnt * 202 dec_6600_intr_evcnt(void *acv, pci_intr_handle_t ih) 203 { 204 205 #if NSIO 206 if (DEC_6600_LINE_IS_ISA(ih)) 207 return (sio_intr_evcnt(NULL /*XXX*/, 208 DEC_6600_LINE_ISA_IRQ(ih))); 209 #endif 210 211 return (alpha_shared_intr_evcnt(dec_6600_pci_intr, ih)); 212 } 213 214 void * 215 dec_6600_intr_establish(void *acv, pci_intr_handle_t ih, int level, int (*func)(void *), void *arg) 216 { 217 void *cookie; 218 219 #if NSIO 220 if (DEC_6600_LINE_IS_ISA(ih)) 221 return (sio_intr_establish(NULL /*XXX*/, 222 DEC_6600_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg)); 223 #endif 224 225 if (ih >= PCI_NIRQ) 226 panic("dec_6600_intr_establish: bogus dec 6600 IRQ 0x%lx", 227 ih); 228 229 cookie = alpha_shared_intr_establish(dec_6600_pci_intr, ih, IST_LEVEL, 230 level, func, arg, irqtype); 231 232 if (cookie != NULL && 233 alpha_shared_intr_firstactive(dec_6600_pci_intr, ih)) { 234 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_6600_iointr, NULL, 235 level); 236 dec_6600_intr_enable(ih); 237 } 238 return (cookie); 239 } 240 241 void 242 dec_6600_intr_disestablish(void *acv, void *cookie) 243 { 244 struct alpha_shared_intrhand *ih = cookie; 245 unsigned int irq = ih->ih_num; 246 int s; 247 248 #if NSIO 249 /* 250 * We have to determine if this is an ISA IRQ or not! We do this 251 * by checking to see if the intrhand points back to an intrhead 252 * that points to the sioprimary TSP. If not, it's an ISA IRQ. 253 * Pretty disgusting, eh? 254 */ 255 if (ih->ih_intrhead->intr_private != sioprimary) { 256 sio_intr_disestablish(NULL /*XXX*/, cookie); 257 return; 258 } 259 #endif 260 261 s = splhigh(); 262 263 alpha_shared_intr_disestablish(dec_6600_pci_intr, cookie, irqtype); 264 if (alpha_shared_intr_isactive(dec_6600_pci_intr, irq) == 0) { 265 dec_6600_intr_disable(irq); 266 alpha_shared_intr_set_dfltsharetype(dec_6600_pci_intr, irq, 267 IST_NONE); 268 scb_free(0x900 + SCB_IDXTOVEC(irq)); 269 } 270 271 splx(s); 272 } 273 274 void 275 dec_6600_iointr(void *arg, unsigned long vec) 276 { 277 int irq; 278 279 irq = SCB_VECTOIDX(vec - 0x900); 280 281 if (irq >= PCI_NIRQ) 282 panic("iointr: irq %d is too high", irq); 283 284 if (!alpha_shared_intr_dispatch(dec_6600_pci_intr, irq)) { 285 alpha_shared_intr_stray(dec_6600_pci_intr, irq, 286 irqtype); 287 if (ALPHA_SHARED_INTR_DISABLE(dec_6600_pci_intr, irq)) 288 dec_6600_intr_disable(irq); 289 } else 290 alpha_shared_intr_reset_strays(dec_6600_pci_intr, irq); 291 } 292 293 void 294 dec_6600_intr_enable(int irq) 295 { 296 alpha_mb(); 297 STQP(TS_C_DIM0) |= 1UL << irq; 298 alpha_mb(); 299 } 300 301 void 302 dec_6600_intr_disable(int irq) 303 { 304 alpha_mb(); 305 STQP(TS_C_DIM0) &= ~(1UL << irq); 306 alpha_mb(); 307 } 308 309 void * 310 dec_6600_pciide_compat_intr_establish(void *v, struct device *dev, 311 const struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg) 312 { 313 pci_chipset_tag_t pc = pa->pa_pc; 314 void *cookie = NULL; 315 int bus, irq; 316 317 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 318 319 /* 320 * If this isn't PCI bus #0 on the TSP that holds the PCI-ISA 321 * bridge, all bets are off. 322 */ 323 if (bus != 0 || pc->pc_intr_v != sioprimary) 324 return (NULL); 325 326 irq = PCIIDE_COMPAT_IRQ(chan); 327 #if NSIO 328 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 329 func, arg); 330 if (cookie == NULL) 331 return (NULL); 332 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 333 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq)); 334 #endif 335 return (cookie); 336 } 337
Indexes created Mon Oct 13 01:09:56 GMT 2025