pci_6600.c revision 1.27
1 /* $NetBSD: pci_6600.c,v 1.27 2020/09/23 18:48:50 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.27 2020/09/23 18:48:50 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <machine/autoconf.h> 45 #define _ALPHA_BUS_DMA_PRIVATE 46 #include <sys/bus.h> 47 #include <machine/rpb.h> 48 #include <machine/alpha.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pciidereg.h> 53 #include <dev/pci/pciidevar.h> 54 55 #include <alpha/pci/tsreg.h> 56 #include <alpha/pci/tsvar.h> 57 #include <alpha/pci/pci_6600.h> 58 59 #define pci_6600() { Generate ctags(1) key. } 60 61 #include "sio.h" 62 #if NSIO 63 #include <alpha/pci/siovar.h> 64 #endif 65 66 #define PCI_NIRQ 64 67 #define PCI_SIO_IRQ 55 68 #define PCI_STRAY_MAX 5 69 70 /* 71 * Some Tsunami models have a PCI device (the USB controller) with interrupts 72 * tied to ISA IRQ lines. The IRQ is encoded as: 73 * 74 * line = 0xe0 | isa_irq; 75 */ 76 #define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef) 77 #define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f) 78 79 static struct tsp_config *sioprimary; 80 81 static void dec_6600_intr_disestablish(pci_chipset_tag_t, void *); 82 static void *dec_6600_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 83 int, int (*func)(void *), void *); 84 static const char *dec_6600_intr_string(pci_chipset_tag_t, pci_intr_handle_t, 85 char *, size_t); 86 static const struct evcnt *dec_6600_intr_evcnt(pci_chipset_tag_t, 87 pci_intr_handle_t); 88 static int dec_6600_intr_map(const struct pci_attach_args *, 89 pci_intr_handle_t *); 90 91 static void *dec_6600_pciide_compat_intr_establish(device_t, 92 const struct pci_attach_args *, int, 93 int (*)(void *), void *); 94 95 static void dec_6600_intr_enable(pci_chipset_tag_t, int irq); 96 static void dec_6600_intr_disable(pci_chipset_tag_t, int irq); 97 98 /* Software copy of enabled interrupt bits. */ 99 static uint64_t dec_6600_intr_enables __read_mostly; 100 101 void 102 pci_6600_pickintr(struct tsp_config *pcp) 103 { 104 bus_space_tag_t iot = &pcp->pc_iot; 105 pci_chipset_tag_t pc = &pcp->pc_pc; 106 char *cp; 107 int i; 108 109 pc->pc_intr_v = pcp; 110 pc->pc_intr_map = dec_6600_intr_map; 111 pc->pc_intr_string = dec_6600_intr_string; 112 pc->pc_intr_evcnt = dec_6600_intr_evcnt; 113 pc->pc_intr_establish = dec_6600_intr_establish; 114 pc->pc_intr_disestablish = dec_6600_intr_disestablish; 115 116 pc->pc_pciide_compat_intr_establish = NULL; 117 118 pc->pc_intr_desc = "dec 6600 irq"; 119 pc->pc_vecbase = 0x900; 120 pc->pc_nirq = PCI_NIRQ; 121 122 pc->pc_intr_enable = dec_6600_intr_enable; 123 pc->pc_intr_disable = dec_6600_intr_disable; 124 125 /* 126 * System-wide and Pchip-0-only logic... 127 */ 128 if (sioprimary == NULL) { 129 sioprimary = pcp; 130 pc->pc_pciide_compat_intr_establish = 131 dec_6600_pciide_compat_intr_establish; 132 #define PCI_6600_IRQ_STR 8 133 pc->pc_shared_intrs = alpha_shared_intr_alloc(PCI_NIRQ, 134 PCI_6600_IRQ_STR); 135 for (i = 0; i < PCI_NIRQ; i++) { 136 alpha_shared_intr_set_maxstrays(pc->pc_shared_intrs, i, 137 PCI_STRAY_MAX); 138 alpha_shared_intr_set_private(pc->pc_shared_intrs, i, 139 sioprimary); 140 141 cp = alpha_shared_intr_string(pc->pc_shared_intrs, i); 142 snprintf(cp, PCI_6600_IRQ_STR, "irq %d", i); 143 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 144 pc->pc_shared_intrs, i), EVCNT_TYPE_INTR, NULL, 145 "dec 6600", cp); 146 } 147 #if NSIO 148 sio_intr_setup(pc, iot); 149 dec_6600_intr_enable(pc, PCI_SIO_IRQ); /* irq line for sio */ 150 #endif 151 } else { 152 pc->pc_shared_intrs = sioprimary->pc_pc.pc_shared_intrs; 153 } 154 } 155 156 static int 157 dec_6600_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 158 { 159 pcitag_t bustag = pa->pa_intrtag; 160 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 161 pci_chipset_tag_t pc = pa->pa_pc; 162 int bus, device, function; 163 164 if (buspin == 0) { 165 /* No IRQ used. */ 166 return 1; 167 } 168 if (buspin < 0 || buspin > 4) { 169 printf("intr_map: bad interrupt pin %d\n", buspin); 170 return 1; 171 } 172 173 pci_decompose_tag(pc, bustag, &bus, &device, &function); 174 175 /* 176 * The console places the interrupt mapping in the "line" value. 177 * A value of (char)-1 indicates there is no mapping. 178 */ 179 if (line == 0xff) { 180 printf("dec_6600_intr_map: no mapping for %d/%d/%d\n", 181 bus, device, function); 182 return (1); 183 } 184 185 #if NSIO == 0 186 if (DEC_6600_LINE_IS_ISA(line)) { 187 printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n", 188 DEC_6600_LINE_ISA_IRQ(line), bus, device, function); 189 return (1); 190 } 191 #endif 192 193 if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= PCI_NIRQ) 194 panic("dec_6600_intr_map: dec 6600 irq too large (%d)", 195 line); 196 197 alpha_pci_intr_handle_init(ihp, line, 0); 198 return (0); 199 } 200 201 static const char * 202 dec_6600_intr_string(pci_chipset_tag_t const pc, pci_intr_handle_t const ih, 203 char * const buf, size_t const len) 204 { 205 #if NSIO 206 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 207 208 if (DEC_6600_LINE_IS_ISA(irq)) 209 return (sio_intr_string(NULL /*XXX*/, 210 DEC_6600_LINE_ISA_IRQ(irq), buf, len)); 211 #endif 212 213 return alpha_pci_generic_intr_string(pc, ih, buf, len); 214 } 215 216 static const struct evcnt * 217 dec_6600_intr_evcnt(pci_chipset_tag_t const pc, pci_intr_handle_t const ih) 218 { 219 #if NSIO 220 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 221 222 if (DEC_6600_LINE_IS_ISA(irq)) 223 return (sio_intr_evcnt(NULL /*XXX*/, 224 DEC_6600_LINE_ISA_IRQ(irq))); 225 #endif 226 227 return alpha_pci_generic_intr_evcnt(pc, ih); 228 } 229 230 static void * 231 dec_6600_intr_establish(pci_chipset_tag_t const pc, pci_intr_handle_t const ih, 232 int const level, int (*func)(void *), void *arg) 233 { 234 #if NSIO 235 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 236 const u_int flags = alpha_pci_intr_handle_get_flags(&ih); 237 238 if (DEC_6600_LINE_IS_ISA(irq)) 239 return (sio_intr_establish(NULL /*XXX*/, 240 DEC_6600_LINE_ISA_IRQ(irq), IST_LEVEL, level, flags, 241 func, arg)); 242 #endif 243 244 return alpha_pci_generic_intr_establish(pc, ih, level, func, arg); 245 } 246 247 static void 248 dec_6600_intr_disestablish(pci_chipset_tag_t const pc, void * const cookie) 249 { 250 #if NSIO 251 struct alpha_shared_intrhand * const ih = cookie; 252 253 /* 254 * We have to determine if this is an ISA IRQ or not! We do this 255 * by checking to see if the intrhand points back to an intrhead 256 * that points to the sioprimary TSP. If not, it's an ISA IRQ. 257 * Pretty disgusting, eh? 258 */ 259 if (ih->ih_intrhead->intr_private != sioprimary) { 260 sio_intr_disestablish(NULL /*XXX*/, cookie); 261 return; 262 } 263 #endif 264 265 return alpha_pci_generic_intr_disestablish(pc, cookie); 266 } 267 268 static void 269 dec_6600_intr_enable(pci_chipset_tag_t const pc __unused, int const irq) 270 { 271 dec_6600_intr_enables |= 1UL << irq; 272 alpha_mb(); 273 STQP(TS_C_DIM0) = dec_6600_intr_enables; 274 alpha_mb(); 275 } 276 277 static void 278 dec_6600_intr_disable(pci_chipset_tag_t const pc __unused, int const irq) 279 { 280 dec_6600_intr_enables &= ~(1UL << irq); 281 alpha_mb(); 282 STQP(TS_C_DIM0) = dec_6600_intr_enables; 283 alpha_mb(); 284 } 285 286 static void * 287 dec_6600_pciide_compat_intr_establish(device_t dev, 288 const struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg) 289 { 290 pci_chipset_tag_t const pc = pa->pa_pc; 291 292 /* 293 * If this isn't the TSP that holds the PCI-ISA bridge, 294 * all bets are off. 295 */ 296 if (pc->pc_intr_v != sioprimary) 297 return (NULL); 298 299 return sio_pciide_compat_intr_establish(dev, pa, chan, func, arg); 300 } 301
Indexes created Mon Oct 13 05:10:05 GMT 2025