pci_6600.c revision 1.3
1 /* $NetBSD: pci_6600.c,v 1.3 2000/06/04 19:14:21 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.3 2000/06/04 19:14:21 cgd Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <vm/vm.h> 44 45 #include <machine/autoconf.h> 46 #define _ALPHA_BUS_DMA_PRIVATE 47 #include <machine/bus.h> 48 #include <machine/rpb.h> 49 #include <machine/intrcnt.h> 50 #include <machine/alpha.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pciidereg.h> 55 #include <dev/pci/pciidevar.h> 56 57 #include <alpha/pci/tsreg.h> 58 #include <alpha/pci/tsvar.h> 59 #include <alpha/pci/pci_6600.h> 60 61 #define pci_6600() { Generate ctags(1) key. } 62 63 #include "sio.h" 64 #if NSIO 65 #include <alpha/pci/siovar.h> 66 #endif 67 68 #define PCI_STRAY_MAX 5 69 #define DEC_6600_MAX_IRQ INTRCNT_OTHER_LEN 70 71 /* 72 * Some Tsunami models have a PCI device (the USB controller) with interrupts 73 * tied to ISA IRQ lines. The IRQ is encoded as: 74 * 75 * line = 0xe0 | isa_irq; 76 */ 77 #define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef) 78 #define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f) 79 80 static char *irqtype = "6600 irq"; 81 static struct tsp_config *sioprimary; 82 83 void dec_6600_intr_disestablish __P((void *, void *)); 84 void *dec_6600_intr_establish __P(( 85 void *, pci_intr_handle_t, int, int (*func)(void *), void *)); 86 const char *dec_6600_intr_string __P((void *, pci_intr_handle_t)); 87 const struct evcnt *dec_6600_intr_evcnt __P((void *, pci_intr_handle_t)); 88 int dec_6600_intr_map __P((void *, pcitag_t, int, int, pci_intr_handle_t *)); 89 void *dec_6600_pciide_compat_intr_establish __P((void *, struct device *, 90 struct pci_attach_args *, int, int (*)(void *), void *)); 91 92 struct alpha_shared_intr *dec_6600_pci_intr; 93 94 void dec_6600_iointr __P((void *framep, unsigned long vec)); 95 extern void dec_6600_intr_enable __P((int irq)); 96 extern void dec_6600_intr_disable __P((int irq)); 97 98 void 99 pci_6600_pickintr(pcp) 100 struct tsp_config *pcp; 101 { 102 bus_space_tag_t iot = &pcp->pc_iot; 103 pci_chipset_tag_t pc = &pcp->pc_pc; 104 int i; 105 106 pc->pc_intr_v = pcp; 107 pc->pc_intr_map = dec_6600_intr_map; 108 pc->pc_intr_string = dec_6600_intr_string; 109 pc->pc_intr_evcnt = dec_6600_intr_evcnt; 110 pc->pc_intr_establish = dec_6600_intr_establish; 111 pc->pc_intr_disestablish = dec_6600_intr_disestablish; 112 pc->pc_pciide_compat_intr_establish = NULL; 113 114 /* 115 * System-wide and Pchip-0-only logic... 116 */ 117 if (dec_6600_pci_intr == NULL) { 118 sioprimary = pcp; 119 pc->pc_pciide_compat_intr_establish = 120 dec_6600_pciide_compat_intr_establish; 121 dec_6600_pci_intr = alpha_shared_intr_alloc(DEC_6600_MAX_IRQ); 122 for (i = 0; i < DEC_6600_MAX_IRQ; i++) { 123 alpha_shared_intr_set_maxstrays(dec_6600_pci_intr, i, 124 PCI_STRAY_MAX); 125 alpha_shared_intr_set_private(dec_6600_pci_intr, i, 126 sioprimary); 127 } 128 #if NSIO 129 sio_intr_setup(pc, iot); 130 dec_6600_intr_enable(55); /* irq line for sio */ 131 #endif 132 set_iointr(dec_6600_iointr); 133 } 134 } 135 136 int 137 dec_6600_intr_map(acv, bustag, buspin, line, ihp) 138 void *acv; 139 pcitag_t bustag; 140 int buspin, line; 141 pci_intr_handle_t *ihp; 142 { 143 struct tsp_config *pcp = acv; 144 pci_chipset_tag_t pc = &pcp->pc_pc; 145 int bus, device, function; 146 147 if (buspin == 0) { 148 /* No IRQ used. */ 149 return 1; 150 } 151 if (buspin > 4) { 152 printf("intr_map: bad interrupt pin %d\n", buspin); 153 return 1; 154 } 155 156 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 157 158 /* 159 * The console places the interrupt mapping in the "line" value. 160 * A value of (char)-1 indicates there is no mapping. 161 */ 162 if (line == 0xff) { 163 printf("dec_6600_intr_map: no mapping for %d/%d/%d\n", 164 bus, device, function); 165 return (1); 166 } 167 168 #if NSIO == 0 169 if (DEC_6600_LINE_IS_ISA(line)) { 170 printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n", 171 DEC_6600_LINE_ISA_IRQ(line), bus, device, function); 172 return (1); 173 } 174 #endif 175 176 if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= DEC_6600_MAX_IRQ) 177 panic("dec_6600_intr_map: dec 6600 irq too large (%d)\n", 178 line); 179 180 *ihp = line; 181 return (0); 182 } 183 184 const char * 185 dec_6600_intr_string(acv, ih) 186 void *acv; 187 pci_intr_handle_t ih; 188 { 189 190 static const char irqfmt[] = "dec 6600 irq %ld"; 191 static char irqstr[sizeof irqfmt]; 192 193 #if NSIO 194 if (DEC_6600_LINE_IS_ISA(ih)) 195 return (sio_intr_string(NULL /*XXX*/, 196 DEC_6600_LINE_ISA_IRQ(ih))); 197 #endif 198 199 snprintf(irqstr, sizeof irqstr, irqfmt, ih); 200 return (irqstr); 201 } 202 203 const struct evcnt * 204 dec_6600_intr_evcnt(acv, ih) 205 void *acv; 206 pci_intr_handle_t ih; 207 { 208 209 #if NSIO 210 if (DEC_6600_LINE_IS_ISA(ih)) 211 return (sio_intr_evcnt(NULL /*XXX*/, 212 DEC_6600_LINE_ISA_IRQ(ih))); 213 #endif 214 215 /* XXX for now, no evcnt parent reported */ 216 return (NULL); 217 } 218 219 void * 220 dec_6600_intr_establish(acv, ih, level, func, arg) 221 void *acv, *arg; 222 pci_intr_handle_t ih; 223 int level; 224 int (*func) __P((void *)); 225 { 226 void *cookie; 227 228 #if NSIO 229 if (DEC_6600_LINE_IS_ISA(ih)) 230 return (sio_intr_establish(NULL /*XXX*/, 231 DEC_6600_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg)); 232 #endif 233 234 if (ih >= DEC_6600_MAX_IRQ) 235 panic("dec_6600_intr_establish: bogus dec 6600 IRQ 0x%lx\n", 236 ih); 237 238 cookie = alpha_shared_intr_establish(dec_6600_pci_intr, ih, IST_LEVEL, 239 level, func, arg, irqtype); 240 241 if (cookie != NULL && alpha_shared_intr_isactive(dec_6600_pci_intr, ih)) 242 dec_6600_intr_enable(ih); 243 return (cookie); 244 } 245 246 void 247 dec_6600_intr_disestablish(acv, cookie) 248 void *acv, *cookie; 249 { 250 struct alpha_shared_intrhand *ih = cookie; 251 unsigned int irq = ih->ih_num; 252 int s; 253 254 #if NSIO 255 /* 256 * We have to determine if this is an ISA IRQ or not! We do this 257 * by checking to see if the intrhand points back to an intrhead 258 * that points to the sioprimary TSP. If not, it's an ISA IRQ. 259 * Pretty disgusting, eh? 260 */ 261 if (ih->ih_intrhead->intr_private != sioprimary) { 262 sio_intr_disestablish(NULL /*XXX*/, cookie); 263 return; 264 } 265 #endif 266 267 s = splhigh(); 268 269 alpha_shared_intr_disestablish(dec_6600_pci_intr, cookie, irqtype); 270 if (alpha_shared_intr_isactive(dec_6600_pci_intr, irq) == 0) { 271 dec_6600_intr_disable(irq); 272 alpha_shared_intr_set_dfltsharetype(dec_6600_pci_intr, irq, 273 IST_NONE); 274 } 275 276 splx(s); 277 } 278 279 void 280 dec_6600_iointr(framep, vec) 281 void *framep; 282 unsigned long vec; 283 { 284 int irq; 285 286 if (vec >= 0x900) { 287 irq = (vec - 0x900) >> 4; 288 289 if(irq >= INTRCNT_OTHER_LEN) 290 panic("iointr: irq %d is too high", irq); 291 ++intrcnt[INTRCNT_OTHER_BASE + irq]; 292 293 if (!alpha_shared_intr_dispatch(dec_6600_pci_intr, irq)) { 294 alpha_shared_intr_stray(dec_6600_pci_intr, irq, 295 irqtype); 296 if (ALPHA_SHARED_INTR_DISABLE(dec_6600_pci_intr, irq)) 297 dec_6600_intr_disable(irq); 298 } 299 return; 300 } 301 #if NSIO 302 if (vec >= 0x800) { 303 sio_iointr(framep, vec); 304 return; 305 } 306 #endif 307 panic("iointr: weird vec 0x%lx\n", vec); 308 } 309 310 void 311 dec_6600_intr_enable(irq) 312 int irq; 313 { 314 alpha_mb(); 315 STQP(TS_C_DIM0) |= 1UL << irq; 316 alpha_mb(); 317 } 318 319 void 320 dec_6600_intr_disable(irq) 321 int irq; 322 { 323 alpha_mb(); 324 STQP(TS_C_DIM0) &= ~(1UL << irq); 325 alpha_mb(); 326 } 327 328 void * 329 dec_6600_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 330 void *v; 331 struct device *dev; 332 struct pci_attach_args *pa; 333 int chan; 334 int (*func) __P((void *)); 335 void *arg; 336 { 337 pci_chipset_tag_t pc = pa->pa_pc; 338 void *cookie = NULL; 339 int bus, irq; 340 341 alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 342 343 /* 344 * If this isn't PCI bus #0 on the TSP that holds the PCI-ISA 345 * bridge, all bets are off. 346 */ 347 if (bus != 0 || pc->pc_intr_v != sioprimary) 348 return (NULL); 349 350 irq = PCIIDE_COMPAT_IRQ(chan); 351 #if NSIO 352 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 353 func, arg); 354 #endif 355 return (cookie); 356 } 357
Indexes created Wed Oct 15 16:09:53 GMT 2025