pci_axppci_33.c revision 1.28 1 1.28 thorpej /* $NetBSD: pci_axppci_33.c,v 1.28 2002/05/15 16:57:42 thorpej Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.4 cgd * Copyright (c) 1995, 1996 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.3 cgd * Authors: Jeffrey Hsu and Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.11 cgd
30 1.12 cgd #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
31 1.12 cgd
32 1.28 thorpej __KERNEL_RCSID(0, "$NetBSD: pci_axppci_33.c,v 1.28 2002/05/15 16:57:42 thorpej Exp $");
33 1.1 cgd
34 1.1 cgd #include <sys/types.h>
35 1.1 cgd #include <sys/param.h>
36 1.1 cgd #include <sys/time.h>
37 1.1 cgd #include <sys/systm.h>
38 1.1 cgd #include <sys/errno.h>
39 1.1 cgd #include <sys/device.h>
40 1.25 mrg
41 1.25 mrg #include <uvm/uvm_extern.h>
42 1.1 cgd
43 1.6 cgd #include <machine/autoconf.h>
44 1.3 cgd #include <machine/bus.h>
45 1.3 cgd #include <machine/intr.h>
46 1.3 cgd
47 1.1 cgd #include <dev/isa/isavar.h>
48 1.1 cgd #include <dev/pci/pcireg.h>
49 1.1 cgd #include <dev/pci/pcivar.h>
50 1.1 cgd
51 1.1 cgd #include <alpha/pci/lcavar.h>
52 1.1 cgd
53 1.1 cgd #include <alpha/pci/pci_axppci_33.h>
54 1.1 cgd #include <alpha/pci/siovar.h>
55 1.5 cgd #include <alpha/pci/sioreg.h>
56 1.1 cgd
57 1.1 cgd #include "sio.h"
58 1.1 cgd
59 1.26 sommerfe int dec_axppci_33_intr_map __P((struct pci_attach_args *, pci_intr_handle_t *));
60 1.3 cgd const char *dec_axppci_33_intr_string __P((void *, pci_intr_handle_t));
61 1.23 cgd const struct evcnt *dec_axppci_33_intr_evcnt __P((void *, pci_intr_handle_t));
62 1.3 cgd void *dec_axppci_33_intr_establish __P((void *, pci_intr_handle_t,
63 1.3 cgd int, int (*func)(void *), void *));
64 1.3 cgd void dec_axppci_33_intr_disestablish __P((void *, void *));
65 1.3 cgd
66 1.5 cgd #define LCA_SIO_DEVICE 7 /* XXX */
67 1.1 cgd
68 1.3 cgd void
69 1.3 cgd pci_axppci_33_pickintr(lcp)
70 1.3 cgd struct lca_config *lcp;
71 1.3 cgd {
72 1.16 thorpej bus_space_tag_t iot = &lcp->lc_iot;
73 1.3 cgd pci_chipset_tag_t pc = &lcp->lc_pc;
74 1.3 cgd pcireg_t sioclass;
75 1.3 cgd int sioII;
76 1.3 cgd
77 1.3 cgd /* XXX MAGIC NUMBER */
78 1.3 cgd sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, LCA_SIO_DEVICE, 0),
79 1.3 cgd PCI_CLASS_REG);
80 1.3 cgd sioII = (sioclass & 0xff) >= 3;
81 1.3 cgd
82 1.3 cgd if (!sioII)
83 1.8 christos printf("WARNING: SIO NOT SIO II... NO BETS...\n");
84 1.3 cgd
85 1.3 cgd pc->pc_intr_v = lcp;
86 1.3 cgd pc->pc_intr_map = dec_axppci_33_intr_map;
87 1.3 cgd pc->pc_intr_string = dec_axppci_33_intr_string;
88 1.23 cgd pc->pc_intr_evcnt = dec_axppci_33_intr_evcnt;
89 1.3 cgd pc->pc_intr_establish = dec_axppci_33_intr_establish;
90 1.3 cgd pc->pc_intr_disestablish = dec_axppci_33_intr_disestablish;
91 1.19 thorpej
92 1.20 mjacob /* Not supported on AXPpci33. */
93 1.19 thorpej pc->pc_pciide_compat_intr_establish = NULL;
94 1.3 cgd
95 1.3 cgd #if NSIO
96 1.17 thorpej sio_intr_setup(pc, iot);
97 1.3 cgd #else
98 1.3 cgd panic("pci_axppci_33_pickintr: no I/O interrupt handler (no sio)");
99 1.3 cgd #endif
100 1.3 cgd }
101 1.3 cgd
102 1.3 cgd int
103 1.26 sommerfe dec_axppci_33_intr_map(pa, ihp)
104 1.26 sommerfe struct pci_attach_args *pa;
105 1.3 cgd pci_intr_handle_t *ihp;
106 1.1 cgd {
107 1.26 sommerfe pcitag_t bustag = pa->pa_intrtag;
108 1.26 sommerfe int buspin = pa->pa_intrpin;
109 1.26 sommerfe pci_chipset_tag_t pc = pa->pa_pc;
110 1.3 cgd int device, pirq;
111 1.3 cgd pcireg_t pirqreg;
112 1.1 cgd u_int8_t pirqline;
113 1.13 cgd
114 1.13 cgd #ifndef DIAGNOSTIC
115 1.13 cgd pirq = 0; /* XXX gcc -Wuninitialized */
116 1.13 cgd #endif
117 1.1 cgd
118 1.21 thorpej if (buspin == 0) {
119 1.21 thorpej /* No IRQ used. */
120 1.21 thorpej return 1;
121 1.21 thorpej }
122 1.21 thorpej if (buspin > 4) {
123 1.21 thorpej printf("dec_axppci_33_intr_map: bad interrupt pin %d\n",
124 1.21 thorpej buspin);
125 1.21 thorpej return 1;
126 1.21 thorpej }
127 1.1 cgd
128 1.28 thorpej pci_decompose_tag(pc, bustag, NULL, &device, NULL);
129 1.1 cgd
130 1.1 cgd switch (device) {
131 1.1 cgd case 6: /* NCR SCSI */
132 1.1 cgd pirq = 3;
133 1.1 cgd break;
134 1.1 cgd
135 1.1 cgd case 11: /* slot 1 */
136 1.3 cgd switch (buspin) {
137 1.1 cgd case PCI_INTERRUPT_PIN_A:
138 1.1 cgd case PCI_INTERRUPT_PIN_D:
139 1.1 cgd pirq = 0;
140 1.1 cgd break;
141 1.1 cgd case PCI_INTERRUPT_PIN_B:
142 1.1 cgd pirq = 2;
143 1.1 cgd break;
144 1.1 cgd case PCI_INTERRUPT_PIN_C:
145 1.1 cgd pirq = 1;
146 1.1 cgd break;
147 1.10 cgd #ifdef DIAGNOSTIC
148 1.10 cgd default: /* XXX gcc -Wuninitialized */
149 1.18 thorpej panic("dec_axppci_33_intr_map: bogus PCI pin %d\n",
150 1.10 cgd buspin);
151 1.10 cgd #endif
152 1.1 cgd };
153 1.1 cgd break;
154 1.1 cgd
155 1.1 cgd case 12: /* slot 2 */
156 1.3 cgd switch (buspin) {
157 1.1 cgd case PCI_INTERRUPT_PIN_A:
158 1.1 cgd case PCI_INTERRUPT_PIN_D:
159 1.1 cgd pirq = 1;
160 1.1 cgd break;
161 1.1 cgd case PCI_INTERRUPT_PIN_B:
162 1.1 cgd pirq = 0;
163 1.1 cgd break;
164 1.1 cgd case PCI_INTERRUPT_PIN_C:
165 1.1 cgd pirq = 2;
166 1.1 cgd break;
167 1.10 cgd #ifdef DIAGNOSTIC
168 1.10 cgd default: /* XXX gcc -Wuninitialized */
169 1.18 thorpej panic("dec_axppci_33_intr_map: bogus PCI pin %d\n",
170 1.10 cgd buspin);
171 1.10 cgd #endif
172 1.1 cgd };
173 1.1 cgd break;
174 1.1 cgd
175 1.1 cgd case 8: /* slot 3 */
176 1.3 cgd switch (buspin) {
177 1.1 cgd case PCI_INTERRUPT_PIN_A:
178 1.1 cgd case PCI_INTERRUPT_PIN_D:
179 1.1 cgd pirq = 2;
180 1.1 cgd break;
181 1.1 cgd case PCI_INTERRUPT_PIN_B:
182 1.1 cgd pirq = 1;
183 1.1 cgd break;
184 1.1 cgd case PCI_INTERRUPT_PIN_C:
185 1.1 cgd pirq = 0;
186 1.1 cgd break;
187 1.10 cgd #ifdef DIAGNOSTIC
188 1.10 cgd default: /* XXX gcc -Wuninitialized */
189 1.18 thorpej panic("dec_axppci_33_intr_map bogus: PCI pin %d\n",
190 1.10 cgd buspin);
191 1.10 cgd #endif
192 1.1 cgd };
193 1.1 cgd break;
194 1.10 cgd
195 1.1 cgd default:
196 1.10 cgd printf("dec_axppci_33_intr_map: weird device number %d\n",
197 1.10 cgd device);
198 1.10 cgd return 1;
199 1.1 cgd }
200 1.1 cgd
201 1.3 cgd pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, LCA_SIO_DEVICE, 0),
202 1.5 cgd SIO_PCIREG_PIRQ_RTCTRL);
203 1.1 cgd #if 0
204 1.18 thorpej printf("dec_axppci_33_intr_map: device %d pin %c: pirq %d, reg = %x\n",
205 1.3 cgd device, '@' + buspin, pirq, pirqreg);
206 1.1 cgd #endif
207 1.1 cgd pirqline = (pirqreg >> (pirq * 8)) & 0xff;
208 1.1 cgd if ((pirqline & 0x80) != 0)
209 1.3 cgd return 1; /* not routed? */
210 1.1 cgd pirqline &= 0xf;
211 1.1 cgd
212 1.1 cgd #if 0
213 1.18 thorpej printf("dec_axppci_33_intr_map: device %d pin %c: mapped to line %d\n",
214 1.3 cgd device, '@' + buspin, pirqline);
215 1.1 cgd #endif
216 1.1 cgd
217 1.3 cgd *ihp = pirqline;
218 1.3 cgd return (0);
219 1.1 cgd }
220 1.1 cgd
221 1.3 cgd const char *
222 1.3 cgd dec_axppci_33_intr_string(lcv, ih)
223 1.3 cgd void *lcv;
224 1.3 cgd pci_intr_handle_t ih;
225 1.1 cgd {
226 1.10 cgd #if 0
227 1.3 cgd struct lca_config *lcp = lcv;
228 1.10 cgd #endif
229 1.1 cgd
230 1.3 cgd return sio_intr_string(NULL /*XXX*/, ih);
231 1.23 cgd }
232 1.23 cgd
233 1.23 cgd const struct evcnt *
234 1.23 cgd dec_axppci_33_intr_evcnt(lcv, ih)
235 1.23 cgd void *lcv;
236 1.23 cgd pci_intr_handle_t ih;
237 1.23 cgd {
238 1.23 cgd #if 0
239 1.23 cgd struct lca_config *lcp = lcv;
240 1.23 cgd #endif
241 1.23 cgd
242 1.23 cgd return sio_intr_evcnt(NULL /*XXX*/, ih);
243 1.1 cgd }
244 1.1 cgd
245 1.3 cgd void *
246 1.3 cgd dec_axppci_33_intr_establish(lcv, ih, level, func, arg)
247 1.3 cgd void *lcv, *arg;
248 1.3 cgd pci_intr_handle_t ih;
249 1.3 cgd int level;
250 1.3 cgd int (*func) __P((void *));
251 1.1 cgd {
252 1.10 cgd #if 0
253 1.3 cgd struct lca_config *lcp = lcv;
254 1.10 cgd #endif
255 1.1 cgd
256 1.3 cgd return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func,
257 1.3 cgd arg);
258 1.3 cgd }
259 1.1 cgd
260 1.3 cgd void
261 1.3 cgd dec_axppci_33_intr_disestablish(lcv, cookie)
262 1.3 cgd void *lcv, *cookie;
263 1.3 cgd {
264 1.10 cgd #if 0
265 1.3 cgd struct lca_config *lcp = lcv;
266 1.10 cgd #endif
267 1.1 cgd
268 1.3 cgd sio_intr_disestablish(NULL /*XXX*/, cookie);
269 1.1 cgd }
270