pci_axppci_33.c revision 1.9 1 1.9 cgd /* $NetBSD: pci_axppci_33.c,v 1.9 1996/10/23 04:12:27 cgd Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.4 cgd * Copyright (c) 1995, 1996 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.3 cgd * Authors: Jeffrey Hsu and Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.1 cgd
30 1.1 cgd #include <sys/types.h>
31 1.1 cgd #include <sys/param.h>
32 1.1 cgd #include <sys/time.h>
33 1.1 cgd #include <sys/systm.h>
34 1.1 cgd #include <sys/errno.h>
35 1.1 cgd #include <sys/device.h>
36 1.1 cgd #include <vm/vm.h>
37 1.1 cgd
38 1.6 cgd #include <machine/autoconf.h>
39 1.3 cgd #include <machine/bus.h>
40 1.3 cgd #include <machine/intr.h>
41 1.3 cgd
42 1.1 cgd #include <dev/isa/isavar.h>
43 1.1 cgd #include <dev/pci/pcireg.h>
44 1.1 cgd #include <dev/pci/pcivar.h>
45 1.1 cgd
46 1.1 cgd #include <alpha/pci/lcavar.h>
47 1.1 cgd
48 1.1 cgd #include <alpha/pci/pci_axppci_33.h>
49 1.1 cgd #include <alpha/pci/siovar.h>
50 1.5 cgd #include <alpha/pci/sioreg.h>
51 1.1 cgd
52 1.1 cgd #include "sio.h"
53 1.1 cgd
54 1.3 cgd int dec_axppci_33_intr_map __P((void *, pcitag_t, int, int,
55 1.3 cgd pci_intr_handle_t *));
56 1.3 cgd const char *dec_axppci_33_intr_string __P((void *, pci_intr_handle_t));
57 1.3 cgd void *dec_axppci_33_intr_establish __P((void *, pci_intr_handle_t,
58 1.3 cgd int, int (*func)(void *), void *));
59 1.3 cgd void dec_axppci_33_intr_disestablish __P((void *, void *));
60 1.3 cgd
61 1.5 cgd #define LCA_SIO_DEVICE 7 /* XXX */
62 1.1 cgd
63 1.3 cgd void
64 1.3 cgd pci_axppci_33_pickintr(lcp)
65 1.3 cgd struct lca_config *lcp;
66 1.3 cgd {
67 1.9 cgd bus_space_tag_t iot = lcp->lc_iot;
68 1.3 cgd pci_chipset_tag_t pc = &lcp->lc_pc;
69 1.3 cgd pcireg_t sioclass;
70 1.3 cgd int sioII;
71 1.3 cgd
72 1.3 cgd /* XXX MAGIC NUMBER */
73 1.3 cgd sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, LCA_SIO_DEVICE, 0),
74 1.3 cgd PCI_CLASS_REG);
75 1.3 cgd sioII = (sioclass & 0xff) >= 3;
76 1.3 cgd
77 1.3 cgd if (!sioII)
78 1.8 christos printf("WARNING: SIO NOT SIO II... NO BETS...\n");
79 1.3 cgd
80 1.3 cgd pc->pc_intr_v = lcp;
81 1.3 cgd pc->pc_intr_map = dec_axppci_33_intr_map;
82 1.3 cgd pc->pc_intr_string = dec_axppci_33_intr_string;
83 1.3 cgd pc->pc_intr_establish = dec_axppci_33_intr_establish;
84 1.3 cgd pc->pc_intr_disestablish = dec_axppci_33_intr_disestablish;
85 1.3 cgd
86 1.3 cgd #if NSIO
87 1.9 cgd sio_intr_setup(iot);
88 1.3 cgd set_iointr(&sio_iointr);
89 1.3 cgd #else
90 1.3 cgd panic("pci_axppci_33_pickintr: no I/O interrupt handler (no sio)");
91 1.3 cgd #endif
92 1.3 cgd }
93 1.3 cgd
94 1.3 cgd int
95 1.3 cgd dec_axppci_33_intr_map(lcv, bustag, buspin, line, ihp)
96 1.1 cgd void *lcv;
97 1.3 cgd pcitag_t bustag;
98 1.3 cgd int buspin, line;
99 1.3 cgd pci_intr_handle_t *ihp;
100 1.1 cgd {
101 1.1 cgd struct lca_config *lcp = lcv;
102 1.3 cgd pci_chipset_tag_t pc = &lcp->lc_pc;
103 1.3 cgd int device, pirq;
104 1.3 cgd pcireg_t pirqreg;
105 1.1 cgd u_int8_t pirqline;
106 1.1 cgd
107 1.3 cgd if (buspin == 0) {
108 1.1 cgd /* No IRQ used. */
109 1.3 cgd return 1;
110 1.1 cgd }
111 1.3 cgd if (buspin > 4) {
112 1.8 christos printf("pci_map_int: bad interrupt pin %d\n", buspin);
113 1.3 cgd return 1;
114 1.1 cgd }
115 1.1 cgd
116 1.3 cgd pci_decompose_tag(pc, bustag, NULL, &device, NULL);
117 1.1 cgd
118 1.1 cgd switch (device) {
119 1.1 cgd case 6: /* NCR SCSI */
120 1.1 cgd pirq = 3;
121 1.1 cgd break;
122 1.1 cgd
123 1.1 cgd case 11: /* slot 1 */
124 1.3 cgd switch (buspin) {
125 1.1 cgd case PCI_INTERRUPT_PIN_A:
126 1.1 cgd case PCI_INTERRUPT_PIN_D:
127 1.1 cgd pirq = 0;
128 1.1 cgd break;
129 1.1 cgd case PCI_INTERRUPT_PIN_B:
130 1.1 cgd pirq = 2;
131 1.1 cgd break;
132 1.1 cgd case PCI_INTERRUPT_PIN_C:
133 1.1 cgd pirq = 1;
134 1.1 cgd break;
135 1.1 cgd };
136 1.1 cgd break;
137 1.1 cgd
138 1.1 cgd case 12: /* slot 2 */
139 1.3 cgd switch (buspin) {
140 1.1 cgd case PCI_INTERRUPT_PIN_A:
141 1.1 cgd case PCI_INTERRUPT_PIN_D:
142 1.1 cgd pirq = 1;
143 1.1 cgd break;
144 1.1 cgd case PCI_INTERRUPT_PIN_B:
145 1.1 cgd pirq = 0;
146 1.1 cgd break;
147 1.1 cgd case PCI_INTERRUPT_PIN_C:
148 1.1 cgd pirq = 2;
149 1.1 cgd break;
150 1.1 cgd };
151 1.1 cgd break;
152 1.1 cgd
153 1.1 cgd case 8: /* slot 3 */
154 1.3 cgd switch (buspin) {
155 1.1 cgd case PCI_INTERRUPT_PIN_A:
156 1.1 cgd case PCI_INTERRUPT_PIN_D:
157 1.1 cgd pirq = 2;
158 1.1 cgd break;
159 1.1 cgd case PCI_INTERRUPT_PIN_B:
160 1.1 cgd pirq = 1;
161 1.1 cgd break;
162 1.1 cgd case PCI_INTERRUPT_PIN_C:
163 1.1 cgd pirq = 0;
164 1.1 cgd break;
165 1.1 cgd };
166 1.1 cgd break;
167 1.1 cgd default:
168 1.8 christos printf("dec_axppci_33_pci_map_int: unknown device %d\n",
169 1.1 cgd device);
170 1.1 cgd panic("dec_axppci_33_pci_map_int: bad device number");
171 1.1 cgd }
172 1.1 cgd
173 1.3 cgd pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, LCA_SIO_DEVICE, 0),
174 1.5 cgd SIO_PCIREG_PIRQ_RTCTRL);
175 1.1 cgd #if 0
176 1.8 christos printf("pci_axppci_33_map_int: device %d pin %c: pirq %d, reg = %x\n",
177 1.3 cgd device, '@' + buspin, pirq, pirqreg);
178 1.1 cgd #endif
179 1.1 cgd pirqline = (pirqreg >> (pirq * 8)) & 0xff;
180 1.1 cgd if ((pirqline & 0x80) != 0)
181 1.3 cgd return 1; /* not routed? */
182 1.1 cgd pirqline &= 0xf;
183 1.1 cgd
184 1.1 cgd #if 0
185 1.8 christos printf("pci_axppci_33_map_int: device %d pin %c: mapped to line %d\n",
186 1.3 cgd device, '@' + buspin, pirqline);
187 1.1 cgd #endif
188 1.1 cgd
189 1.3 cgd *ihp = pirqline;
190 1.3 cgd return (0);
191 1.1 cgd }
192 1.1 cgd
193 1.3 cgd const char *
194 1.3 cgd dec_axppci_33_intr_string(lcv, ih)
195 1.3 cgd void *lcv;
196 1.3 cgd pci_intr_handle_t ih;
197 1.1 cgd {
198 1.3 cgd struct lca_config *lcp = lcv;
199 1.1 cgd
200 1.3 cgd return sio_intr_string(NULL /*XXX*/, ih);
201 1.1 cgd }
202 1.1 cgd
203 1.3 cgd void *
204 1.3 cgd dec_axppci_33_intr_establish(lcv, ih, level, func, arg)
205 1.3 cgd void *lcv, *arg;
206 1.3 cgd pci_intr_handle_t ih;
207 1.3 cgd int level;
208 1.3 cgd int (*func) __P((void *));
209 1.1 cgd {
210 1.3 cgd struct lca_config *lcp = lcv;
211 1.1 cgd
212 1.3 cgd return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func,
213 1.3 cgd arg);
214 1.3 cgd }
215 1.1 cgd
216 1.3 cgd void
217 1.3 cgd dec_axppci_33_intr_disestablish(lcv, cookie)
218 1.3 cgd void *lcv, *cookie;
219 1.3 cgd {
220 1.3 cgd struct lca_config *lcp = lcv;
221 1.1 cgd
222 1.3 cgd sio_intr_disestablish(NULL /*XXX*/, cookie);
223 1.1 cgd }
224