pci_bwx_bus_mem_chipdep.c revision 1.1
1 /* $NetBSD: pci_bwx_bus_mem_chipdep.c,v 1.1 1998/06/04 21:34:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_MEM_BASE Mem space base to use. 74 * CHIP_MEM_EX_STORE 75 * If defined, device-provided static storage area 76 * for the memory space extent. If this is 77 * defined, CHIP_MEM_EX_STORE_SIZE must also be 78 * defined. If this is not defined, a static area 79 * will be declared. 80 * CHIP_MEM_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #define __C(A,B) __CONCAT(A,B) 88 #define __S(S) __STRING(S) 89 90 /* mapping/unmapping */ 91 int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int, 92 bus_space_handle_t *)); 93 void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t, 94 bus_size_t)); 95 int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t, 96 bus_size_t, bus_size_t, bus_space_handle_t *)); 97 98 /* allocation/deallocation */ 99 int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t, 100 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 101 bus_space_handle_t *)); 102 void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t, 103 bus_size_t)); 104 105 /* barrier */ 106 inline void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t, 107 bus_size_t, bus_size_t, int)); 108 109 /* read (single) */ 110 inline u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t, 111 bus_size_t)); 112 inline u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t, 113 bus_size_t)); 114 inline u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t, 115 bus_size_t)); 116 inline u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t, 117 bus_size_t)); 118 119 /* read multiple */ 120 void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t, 121 bus_size_t, u_int8_t *, bus_size_t)); 122 void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t, 123 bus_size_t, u_int16_t *, bus_size_t)); 124 void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t, 125 bus_size_t, u_int32_t *, bus_size_t)); 126 void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t, 127 bus_size_t, u_int64_t *, bus_size_t)); 128 129 /* read region */ 130 void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t, 131 bus_size_t, u_int8_t *, bus_size_t)); 132 void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t, 133 bus_size_t, u_int16_t *, bus_size_t)); 134 void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int32_t *, bus_size_t)); 136 void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int64_t *, bus_size_t)); 138 139 /* write (single) */ 140 inline void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int8_t)); 142 inline void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int16_t)); 144 inline void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t, 145 bus_size_t, u_int32_t)); 146 inline void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int64_t)); 148 149 /* write multiple */ 150 void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t, 151 bus_size_t, const u_int8_t *, bus_size_t)); 152 void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t, 153 bus_size_t, const u_int16_t *, bus_size_t)); 154 void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t, 155 bus_size_t, const u_int32_t *, bus_size_t)); 156 void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t, 157 bus_size_t, const u_int64_t *, bus_size_t)); 158 159 /* write region */ 160 void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t, 161 bus_size_t, const u_int8_t *, bus_size_t)); 162 void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t, 163 bus_size_t, const u_int16_t *, bus_size_t)); 164 void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t, 165 bus_size_t, const u_int32_t *, bus_size_t)); 166 void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int64_t *, bus_size_t)); 168 169 /* set multiple */ 170 void __C(CHIP,_mem_set_multi_1) __P((void *, bus_space_handle_t, 171 bus_size_t, u_int8_t, bus_size_t)); 172 void __C(CHIP,_mem_set_multi_2) __P((void *, bus_space_handle_t, 173 bus_size_t, u_int16_t, bus_size_t)); 174 void __C(CHIP,_mem_set_multi_4) __P((void *, bus_space_handle_t, 175 bus_size_t, u_int32_t, bus_size_t)); 176 void __C(CHIP,_mem_set_multi_8) __P((void *, bus_space_handle_t, 177 bus_size_t, u_int64_t, bus_size_t)); 178 179 /* set region */ 180 void __C(CHIP,_mem_set_region_1) __P((void *, bus_space_handle_t, 181 bus_size_t, u_int8_t, bus_size_t)); 182 void __C(CHIP,_mem_set_region_2) __P((void *, bus_space_handle_t, 183 bus_size_t, u_int16_t, bus_size_t)); 184 void __C(CHIP,_mem_set_region_4) __P((void *, bus_space_handle_t, 185 bus_size_t, u_int32_t, bus_size_t)); 186 void __C(CHIP,_mem_set_region_8) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int64_t, bus_size_t)); 188 189 /* copy */ 190 void __C(CHIP,_mem_copy_region_1) __P((void *, bus_space_handle_t, 191 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 192 void __C(CHIP,_mem_copy_region_2) __P((void *, bus_space_handle_t, 193 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 194 void __C(CHIP,_mem_copy_region_4) __P((void *, bus_space_handle_t, 195 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 196 void __C(CHIP,_mem_copy_region_8) __P((void *, bus_space_handle_t, 197 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 198 199 #ifndef CHIP_MEM_EX_STORE 200 static long 201 __C(CHIP,_mem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 202 #define CHIP_MEM_EX_STORE(v) (__C(CHIP,_mem_ex_storage)) 203 #define CHIP_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_mem_ex_storage)) 204 #endif 205 206 void 207 __C(CHIP,_bus_mem_init)(t, v) 208 bus_space_tag_t t; 209 void *v; 210 { 211 struct extent *ex; 212 213 /* 214 * Initialize the bus space tag. 215 */ 216 217 /* cookie */ 218 t->abs_cookie = v; 219 220 /* mapping/unmapping */ 221 t->abs_map = __C(CHIP,_mem_map); 222 t->abs_unmap = __C(CHIP,_mem_unmap); 223 t->abs_subregion = __C(CHIP,_mem_subregion); 224 225 /* allocation/deallocation */ 226 t->abs_alloc = __C(CHIP,_mem_alloc); 227 t->abs_free = __C(CHIP,_mem_free); 228 229 /* barrier */ 230 t->abs_barrier = __C(CHIP,_mem_barrier); 231 232 /* read (single) */ 233 t->abs_r_1 = __C(CHIP,_mem_read_1); 234 t->abs_r_2 = __C(CHIP,_mem_read_2); 235 t->abs_r_4 = __C(CHIP,_mem_read_4); 236 t->abs_r_8 = __C(CHIP,_mem_read_8); 237 238 /* read multiple */ 239 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1); 240 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2); 241 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4); 242 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8); 243 244 /* read region */ 245 t->abs_rr_1 = __C(CHIP,_mem_read_region_1); 246 t->abs_rr_2 = __C(CHIP,_mem_read_region_2); 247 t->abs_rr_4 = __C(CHIP,_mem_read_region_4); 248 t->abs_rr_8 = __C(CHIP,_mem_read_region_8); 249 250 /* write (single) */ 251 t->abs_w_1 = __C(CHIP,_mem_write_1); 252 t->abs_w_2 = __C(CHIP,_mem_write_2); 253 t->abs_w_4 = __C(CHIP,_mem_write_4); 254 t->abs_w_8 = __C(CHIP,_mem_write_8); 255 256 /* write multiple */ 257 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1); 258 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2); 259 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4); 260 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8); 261 262 /* write region */ 263 t->abs_wr_1 = __C(CHIP,_mem_write_region_1); 264 t->abs_wr_2 = __C(CHIP,_mem_write_region_2); 265 t->abs_wr_4 = __C(CHIP,_mem_write_region_4); 266 t->abs_wr_8 = __C(CHIP,_mem_write_region_8); 267 268 /* set multiple */ 269 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1); 270 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2); 271 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4); 272 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8); 273 274 /* set region */ 275 t->abs_sr_1 = __C(CHIP,_mem_set_region_1); 276 t->abs_sr_2 = __C(CHIP,_mem_set_region_2); 277 t->abs_sr_4 = __C(CHIP,_mem_set_region_4); 278 t->abs_sr_8 = __C(CHIP,_mem_set_region_8); 279 280 /* copy */ 281 t->abs_c_1 = __C(CHIP,_mem_copy_region_1); 282 t->abs_c_2 = __C(CHIP,_mem_copy_region_2); 283 t->abs_c_4 = __C(CHIP,_mem_copy_region_4); 284 t->abs_c_8 = __C(CHIP,_mem_copy_region_8); 285 286 ex = extent_create(__S(__C(CHIP,_bus_mem)), 0x0UL, 0xffffffffUL, 287 M_DEVBUF, (caddr_t)CHIP_MEM_EX_STORE(v), CHIP_MEM_EX_STORE_SIZE(v), 288 EX_NOWAIT|EX_NOCOALESCE); 289 290 CHIP_MEM_EXTENT(v) = ex; 291 } 292 293 int 294 __C(CHIP,_mem_map)(v, memaddr, memsize, flags, memhp) 295 void *v; 296 bus_addr_t memaddr; 297 bus_size_t memsize; 298 int flags; 299 bus_space_handle_t *memhp; 300 { 301 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; 302 int linear = flags & BUS_SPACE_MAP_LINEAR; 303 int error; 304 305 /* Requests for linear uncacheable space can't be satisfied. */ 306 if (linear && !cacheable) 307 return (EOPNOTSUPP); 308 309 #ifdef EXTENT_DEBUG 310 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr, 311 memaddr + memsize - 1); 312 #endif 313 error = extent_alloc_region(CHIP_MEM_EXTENT(v), memaddr, memsize, 314 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 315 if (error) { 316 #ifdef EXTENT_DEBUG 317 printf("mem: allocation failed (%d)\n", error); 318 extent_print(CHIP_MEM_EXTENT(v)); 319 #endif 320 return (error); 321 } 322 323 *memhp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 324 325 return (0); 326 } 327 328 void 329 __C(CHIP,_mem_unmap)(v, memh, memsize) 330 void *v; 331 bus_space_handle_t memh; 332 bus_size_t memsize; 333 { 334 bus_addr_t memaddr; 335 int error; 336 337 #ifdef EXTENT_DEBUG 338 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize); 339 #endif 340 341 memaddr = memh - ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)); 342 343 #ifdef EXTENT_DEBUG 344 printf("mem: freeing 0x%lx to 0x%lx\n", memaddr, memaddr + memsize - 1); 345 #endif 346 347 error = extent_free(CHIP_MEM_EXTENT(v), memaddr, memsize, 348 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 349 if (error) { 350 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 351 __S(__C(CHIP,_mem_unmap)), memaddr, memaddr + memsize - 1, 352 error); 353 #ifdef EXTENT_DEBUG 354 extent_print(CHIP_MEM_EXTENT(v)); 355 #endif 356 } 357 } 358 359 int 360 __C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh) 361 void *v; 362 bus_space_handle_t memh, *nmemh; 363 bus_size_t offset, size; 364 { 365 366 *nmemh = memh + offset; 367 return (0); 368 } 369 370 int 371 __C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, flags, 372 addrp, bshp) 373 void *v; 374 bus_addr_t rstart, rend, *addrp; 375 bus_size_t size, align, boundary; 376 int flags; 377 bus_space_handle_t *bshp; 378 { 379 380 /* XXX XXX XXX XXX XXX XXX */ 381 panic("%s not implemented", __S(__C(CHIP,_mem_alloc))); 382 } 383 384 void 385 __C(CHIP,_mem_free)(v, bsh, size) 386 void *v; 387 bus_space_handle_t bsh; 388 bus_size_t size; 389 { 390 391 /* XXX XXX XXX XXX XXX XXX */ 392 panic("%s not implemented", __S(__C(CHIP,_mem_free))); 393 } 394 395 inline void 396 __C(CHIP,_mem_barrier)(v, h, o, l, f) 397 void *v; 398 bus_space_handle_t h; 399 bus_size_t o, l; 400 int f; 401 { 402 403 if ((f & BUS_SPACE_BARRIER_READ) != 0) 404 alpha_mb(); 405 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 406 alpha_wmb(); 407 } 408 409 inline u_int8_t 410 __C(CHIP,_mem_read_1)(v, memh, off) 411 void *v; 412 bus_space_handle_t memh; 413 bus_size_t off; 414 { 415 bus_addr_t addr; 416 417 addr = memh + off; 418 alpha_mb(); 419 return (alpha_ldbu((u_int8_t *)addr)); 420 } 421 422 inline u_int16_t 423 __C(CHIP,_mem_read_2)(v, memh, off) 424 void *v; 425 bus_space_handle_t memh; 426 bus_size_t off; 427 { 428 bus_addr_t addr; 429 430 addr = memh + off; 431 #ifdef DIAGNOSTIC 432 if (addr & 1) 433 panic(__S(__C(CHIP,_mem_read_2)) ": addr 0x%lx not aligned", 434 addr); 435 #endif 436 alpha_mb(); 437 return (alpha_ldwu((u_int16_t *)addr)); 438 } 439 440 inline u_int32_t 441 __C(CHIP,_mem_read_4)(v, memh, off) 442 void *v; 443 bus_space_handle_t memh; 444 bus_size_t off; 445 { 446 bus_addr_t addr; 447 448 addr = memh + off; 449 #ifdef DIAGNOSTIC 450 if (addr & 3) 451 panic(__S(__C(CHIP,_mem_read_4)) ": addr 0x%lx not aligned", 452 addr); 453 #endif 454 alpha_mb(); 455 return (*(u_int32_t *)addr); 456 } 457 458 inline u_int64_t 459 __C(CHIP,_mem_read_8)(v, memh, off) 460 void *v; 461 bus_space_handle_t memh; 462 bus_size_t off; 463 { 464 465 alpha_mb(); 466 467 /* XXX XXX XXX */ 468 panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); 469 } 470 471 #define CHIP_mem_read_multi_N(BYTES,TYPE) \ 472 void \ 473 __C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \ 474 void *v; \ 475 bus_space_handle_t h; \ 476 bus_size_t o, c; \ 477 TYPE *a; \ 478 { \ 479 \ 480 while (c-- > 0) { \ 481 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 482 BUS_BARRIER_READ); \ 483 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 484 } \ 485 } 486 CHIP_mem_read_multi_N(1,u_int8_t) 487 CHIP_mem_read_multi_N(2,u_int16_t) 488 CHIP_mem_read_multi_N(4,u_int32_t) 489 CHIP_mem_read_multi_N(8,u_int64_t) 490 491 #define CHIP_mem_read_region_N(BYTES,TYPE) \ 492 void \ 493 __C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \ 494 void *v; \ 495 bus_space_handle_t h; \ 496 bus_size_t o, c; \ 497 TYPE *a; \ 498 { \ 499 \ 500 while (c-- > 0) { \ 501 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 502 o += sizeof *a; \ 503 } \ 504 } 505 CHIP_mem_read_region_N(1,u_int8_t) 506 CHIP_mem_read_region_N(2,u_int16_t) 507 CHIP_mem_read_region_N(4,u_int32_t) 508 CHIP_mem_read_region_N(8,u_int64_t) 509 510 inline void 511 __C(CHIP,_mem_write_1)(v, memh, off, val) 512 void *v; 513 bus_space_handle_t memh; 514 bus_size_t off; 515 u_int8_t val; 516 { 517 bus_addr_t addr; 518 519 addr = memh + off; 520 alpha_stb((u_int8_t *)addr, val); 521 alpha_mb(); 522 } 523 524 inline void 525 __C(CHIP,_mem_write_2)(v, memh, off, val) 526 void *v; 527 bus_space_handle_t memh; 528 bus_size_t off; 529 u_int16_t val; 530 { 531 bus_addr_t addr; 532 533 addr = memh + off; 534 #ifdef DIAGNOSTIC 535 if (addr & 1) 536 panic(__S(__C(CHIP,_mem_write_2)) ": addr 0x%lx not aligned", 537 addr); 538 #endif 539 alpha_stw((u_int16_t *)addr, val); 540 alpha_mb(); 541 } 542 543 inline void 544 __C(CHIP,_mem_write_4)(v, memh, off, val) 545 void *v; 546 bus_space_handle_t memh; 547 bus_size_t off; 548 u_int32_t val; 549 { 550 bus_addr_t addr; 551 552 addr = memh + off; 553 #ifdef DIAGNOSTIC 554 if (addr & 3) 555 panic(__S(__C(CHIP,_mem_write_4)) ": addr 0x%lx not aligned", 556 addr); 557 #endif 558 *(u_int32_t *)addr = val; 559 alpha_mb(); 560 } 561 562 inline void 563 __C(CHIP,_mem_write_8)(v, memh, off, val) 564 void *v; 565 bus_space_handle_t memh; 566 bus_size_t off; 567 u_int64_t val; 568 { 569 570 /* XXX XXX XXX */ 571 panic("%s not implemented", __S(__C(CHIP,_mem_write_8))); 572 alpha_mb(); 573 } 574 575 #define CHIP_mem_write_multi_N(BYTES,TYPE) \ 576 void \ 577 __C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \ 578 void *v; \ 579 bus_space_handle_t h; \ 580 bus_size_t o, c; \ 581 const TYPE *a; \ 582 { \ 583 \ 584 while (c-- > 0) { \ 585 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 586 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 587 BUS_BARRIER_WRITE); \ 588 } \ 589 } 590 CHIP_mem_write_multi_N(1,u_int8_t) 591 CHIP_mem_write_multi_N(2,u_int16_t) 592 CHIP_mem_write_multi_N(4,u_int32_t) 593 CHIP_mem_write_multi_N(8,u_int64_t) 594 595 #define CHIP_mem_write_region_N(BYTES,TYPE) \ 596 void \ 597 __C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \ 598 void *v; \ 599 bus_space_handle_t h; \ 600 bus_size_t o, c; \ 601 const TYPE *a; \ 602 { \ 603 \ 604 while (c-- > 0) { \ 605 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 606 o += sizeof *a; \ 607 } \ 608 } 609 CHIP_mem_write_region_N(1,u_int8_t) 610 CHIP_mem_write_region_N(2,u_int16_t) 611 CHIP_mem_write_region_N(4,u_int32_t) 612 CHIP_mem_write_region_N(8,u_int64_t) 613 614 #define CHIP_mem_set_multi_N(BYTES,TYPE) \ 615 void \ 616 __C(__C(CHIP,_mem_set_multi_),BYTES)(v, h, o, val, c) \ 617 void *v; \ 618 bus_space_handle_t h; \ 619 bus_size_t o, c; \ 620 TYPE val; \ 621 { \ 622 \ 623 while (c-- > 0) { \ 624 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 625 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \ 626 BUS_BARRIER_WRITE); \ 627 } \ 628 } 629 CHIP_mem_set_multi_N(1,u_int8_t) 630 CHIP_mem_set_multi_N(2,u_int16_t) 631 CHIP_mem_set_multi_N(4,u_int32_t) 632 CHIP_mem_set_multi_N(8,u_int64_t) 633 634 #define CHIP_mem_set_region_N(BYTES,TYPE) \ 635 void \ 636 __C(__C(CHIP,_mem_set_region_),BYTES)(v, h, o, val, c) \ 637 void *v; \ 638 bus_space_handle_t h; \ 639 bus_size_t o, c; \ 640 TYPE val; \ 641 { \ 642 \ 643 while (c-- > 0) { \ 644 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 645 o += sizeof val; \ 646 } \ 647 } 648 CHIP_mem_set_region_N(1,u_int8_t) 649 CHIP_mem_set_region_N(2,u_int16_t) 650 CHIP_mem_set_region_N(4,u_int32_t) 651 CHIP_mem_set_region_N(8,u_int64_t) 652 653 #define CHIP_mem_copy_region_N(BYTES) \ 654 void \ 655 __C(__C(CHIP,_mem_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 656 void *v; \ 657 bus_space_handle_t h1, h2; \ 658 bus_size_t o1, o2, c; \ 659 { \ 660 bus_size_t o; \ 661 \ 662 if ((h1 + o1) >= (h2 + o2)) { \ 663 /* src after dest: copy forward */ \ 664 for (o = 0; c != 0; c--, o += BYTES) { \ 665 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 666 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 667 } \ 668 } else { \ 669 /* dest after src: copy backwards */ \ 670 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) { \ 671 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 672 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 673 } \ 674 } \ 675 } 676 CHIP_mem_copy_region_N(1) 677 CHIP_mem_copy_region_N(2) 678 CHIP_mem_copy_region_N(4) 679 CHIP_mem_copy_region_N(8) 680
Indexes created Tue Oct 28 12:10:06 GMT 2025