pci_bwx_bus_mem_chipdep.c revision 1.13
1 /* $NetBSD: pci_bwx_bus_mem_chipdep.c,v 1.13 2000/11/29 05:53:29 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_MEM_BASE Mem space base to use. 74 * CHIP_MEM_EX_STORE 75 * If defined, device-provided static storage area 76 * for the memory space extent. If this is 77 * defined, CHIP_MEM_EX_STORE_SIZE must also be 78 * defined. If this is not defined, a static area 79 * will be declared. 80 * CHIP_MEM_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #include <machine/bwx.h> 88 89 #define __C(A,B) __CONCAT(A,B) 90 #define __S(S) __STRING(S) 91 92 /* mapping/unmapping */ 93 int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int, 94 bus_space_handle_t *, int)); 95 void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t, 96 bus_size_t, int)); 97 int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t, 98 bus_size_t, bus_size_t, bus_space_handle_t *)); 99 100 int __C(CHIP,_mem_translate) __P((void *, bus_addr_t, bus_size_t, 101 int, struct alpha_bus_space_translation *)); 102 int __C(CHIP,_mem_get_window) __P((void *, int, 103 struct alpha_bus_space_translation *)); 104 105 /* allocation/deallocation */ 106 int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t, 107 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 108 bus_space_handle_t *)); 109 void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t, 110 bus_size_t)); 111 112 /* get kernel virtual address */ 113 void * __C(CHIP,_mem_vaddr) __P((void *, bus_space_handle_t)); 114 115 /* barrier */ 116 inline void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t, 117 bus_size_t, bus_size_t, int)); 118 119 /* read (single) */ 120 inline u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t, 121 bus_size_t)); 122 inline u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t, 123 bus_size_t)); 124 inline u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t, 125 bus_size_t)); 126 inline u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t, 127 bus_size_t)); 128 129 /* read multiple */ 130 void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t, 131 bus_size_t, u_int8_t *, bus_size_t)); 132 void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t, 133 bus_size_t, u_int16_t *, bus_size_t)); 134 void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int32_t *, bus_size_t)); 136 void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int64_t *, bus_size_t)); 138 139 /* read region */ 140 void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int8_t *, bus_size_t)); 142 void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int16_t *, bus_size_t)); 144 void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t, 145 bus_size_t, u_int32_t *, bus_size_t)); 146 void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int64_t *, bus_size_t)); 148 149 /* write (single) */ 150 inline void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t, 151 bus_size_t, u_int8_t)); 152 inline void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t, 153 bus_size_t, u_int16_t)); 154 inline void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t, 155 bus_size_t, u_int32_t)); 156 inline void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t, 157 bus_size_t, u_int64_t)); 158 159 /* write multiple */ 160 void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t, 161 bus_size_t, const u_int8_t *, bus_size_t)); 162 void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t, 163 bus_size_t, const u_int16_t *, bus_size_t)); 164 void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t, 165 bus_size_t, const u_int32_t *, bus_size_t)); 166 void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int64_t *, bus_size_t)); 168 169 /* write region */ 170 void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t, 171 bus_size_t, const u_int8_t *, bus_size_t)); 172 void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t, 173 bus_size_t, const u_int16_t *, bus_size_t)); 174 void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t, 175 bus_size_t, const u_int32_t *, bus_size_t)); 176 void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t, 177 bus_size_t, const u_int64_t *, bus_size_t)); 178 179 /* set multiple */ 180 void __C(CHIP,_mem_set_multi_1) __P((void *, bus_space_handle_t, 181 bus_size_t, u_int8_t, bus_size_t)); 182 void __C(CHIP,_mem_set_multi_2) __P((void *, bus_space_handle_t, 183 bus_size_t, u_int16_t, bus_size_t)); 184 void __C(CHIP,_mem_set_multi_4) __P((void *, bus_space_handle_t, 185 bus_size_t, u_int32_t, bus_size_t)); 186 void __C(CHIP,_mem_set_multi_8) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int64_t, bus_size_t)); 188 189 /* set region */ 190 void __C(CHIP,_mem_set_region_1) __P((void *, bus_space_handle_t, 191 bus_size_t, u_int8_t, bus_size_t)); 192 void __C(CHIP,_mem_set_region_2) __P((void *, bus_space_handle_t, 193 bus_size_t, u_int16_t, bus_size_t)); 194 void __C(CHIP,_mem_set_region_4) __P((void *, bus_space_handle_t, 195 bus_size_t, u_int32_t, bus_size_t)); 196 void __C(CHIP,_mem_set_region_8) __P((void *, bus_space_handle_t, 197 bus_size_t, u_int64_t, bus_size_t)); 198 199 /* copy */ 200 void __C(CHIP,_mem_copy_region_1) __P((void *, bus_space_handle_t, 201 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 202 void __C(CHIP,_mem_copy_region_2) __P((void *, bus_space_handle_t, 203 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 204 void __C(CHIP,_mem_copy_region_4) __P((void *, bus_space_handle_t, 205 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 206 void __C(CHIP,_mem_copy_region_8) __P((void *, bus_space_handle_t, 207 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 208 209 #ifndef CHIP_MEM_EX_STORE 210 static long 211 __C(CHIP,_mem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 212 #define CHIP_MEM_EX_STORE(v) (__C(CHIP,_mem_ex_storage)) 213 #define CHIP_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_mem_ex_storage)) 214 #endif 215 216 void 217 __C(CHIP,_bus_mem_init)(t, v) 218 bus_space_tag_t t; 219 void *v; 220 { 221 struct extent *ex; 222 223 /* 224 * Initialize the bus space tag. 225 */ 226 227 /* cookie */ 228 t->abs_cookie = v; 229 230 /* mapping/unmapping */ 231 t->abs_map = __C(CHIP,_mem_map); 232 t->abs_unmap = __C(CHIP,_mem_unmap); 233 t->abs_subregion = __C(CHIP,_mem_subregion); 234 235 t->abs_translate = __C(CHIP,_mem_translate); 236 t->abs_get_window = __C(CHIP,_mem_get_window); 237 238 /* allocation/deallocation */ 239 t->abs_alloc = __C(CHIP,_mem_alloc); 240 t->abs_free = __C(CHIP,_mem_free); 241 242 /* get kernel virtual address */ 243 t->abs_vaddr = __C(CHIP,_mem_vaddr); 244 245 /* barrier */ 246 t->abs_barrier = __C(CHIP,_mem_barrier); 247 248 /* read (single) */ 249 t->abs_r_1 = __C(CHIP,_mem_read_1); 250 t->abs_r_2 = __C(CHIP,_mem_read_2); 251 t->abs_r_4 = __C(CHIP,_mem_read_4); 252 t->abs_r_8 = __C(CHIP,_mem_read_8); 253 254 /* read multiple */ 255 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1); 256 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2); 257 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4); 258 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8); 259 260 /* read region */ 261 t->abs_rr_1 = __C(CHIP,_mem_read_region_1); 262 t->abs_rr_2 = __C(CHIP,_mem_read_region_2); 263 t->abs_rr_4 = __C(CHIP,_mem_read_region_4); 264 t->abs_rr_8 = __C(CHIP,_mem_read_region_8); 265 266 /* write (single) */ 267 t->abs_w_1 = __C(CHIP,_mem_write_1); 268 t->abs_w_2 = __C(CHIP,_mem_write_2); 269 t->abs_w_4 = __C(CHIP,_mem_write_4); 270 t->abs_w_8 = __C(CHIP,_mem_write_8); 271 272 /* write multiple */ 273 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1); 274 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2); 275 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4); 276 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8); 277 278 /* write region */ 279 t->abs_wr_1 = __C(CHIP,_mem_write_region_1); 280 t->abs_wr_2 = __C(CHIP,_mem_write_region_2); 281 t->abs_wr_4 = __C(CHIP,_mem_write_region_4); 282 t->abs_wr_8 = __C(CHIP,_mem_write_region_8); 283 284 /* set multiple */ 285 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1); 286 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2); 287 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4); 288 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8); 289 290 /* set region */ 291 t->abs_sr_1 = __C(CHIP,_mem_set_region_1); 292 t->abs_sr_2 = __C(CHIP,_mem_set_region_2); 293 t->abs_sr_4 = __C(CHIP,_mem_set_region_4); 294 t->abs_sr_8 = __C(CHIP,_mem_set_region_8); 295 296 /* copy */ 297 t->abs_c_1 = __C(CHIP,_mem_copy_region_1); 298 t->abs_c_2 = __C(CHIP,_mem_copy_region_2); 299 t->abs_c_4 = __C(CHIP,_mem_copy_region_4); 300 t->abs_c_8 = __C(CHIP,_mem_copy_region_8); 301 302 ex = extent_create(__S(__C(CHIP,_bus_mem)), 0x0UL, 0xffffffffUL, 303 M_DEVBUF, (caddr_t)CHIP_MEM_EX_STORE(v), CHIP_MEM_EX_STORE_SIZE(v), 304 EX_NOWAIT|EX_NOCOALESCE); 305 306 CHIP_MEM_EXTENT(v) = ex; 307 308 #ifdef CHIP_MEM_INIT_HOOK 309 /* Call chip-specific init function. */ 310 CHIP_MEM_INIT_HOOK(t, v); 311 #endif 312 } 313 314 int 315 __C(CHIP,_mem_translate)(v, memaddr, memlen, flags, abst) 316 void *v; 317 bus_addr_t memaddr; 318 bus_size_t memlen; 319 int flags; 320 struct alpha_bus_space_translation *abst; 321 { 322 323 /* XXX */ 324 return (EOPNOTSUPP); 325 } 326 327 int 328 __C(CHIP,_mem_get_window)(v, window, abst) 329 void *v; 330 int window; 331 struct alpha_bus_space_translation *abst; 332 { 333 334 switch (window) { 335 case 0: 336 abst->abst_bus_start = 0; 337 abst->abst_bus_end = 0xffffffffUL; 338 abst->abst_sys_start = CHIP_MEM_SYS_START(v); 339 abst->abst_sys_end = CHIP_MEM_SYS_START(v) + abst->abst_bus_end; 340 abst->abst_addr_shift = 0; 341 abst->abst_size_shift = 0; 342 abst->abst_flags = ABST_DENSE|ABST_BWX; 343 break; 344 345 default: 346 panic(__S(__C(CHIP,_mem_get_window)) ": invalid window %d", 347 window); 348 } 349 350 return (0); 351 } 352 353 int 354 __C(CHIP,_mem_map)(v, memaddr, memsize, flags, memhp, acct) 355 void *v; 356 bus_addr_t memaddr; 357 bus_size_t memsize; 358 int flags; 359 bus_space_handle_t *memhp; 360 int acct; 361 { 362 int prefetchable = flags & BUS_SPACE_MAP_PREFETCHABLE; 363 int linear = flags & BUS_SPACE_MAP_LINEAR; 364 int error; 365 366 /* Requests for linear unprefetchable space can't be satisfied. */ 367 if (linear && !prefetchable) 368 return (EOPNOTSUPP); 369 370 if (acct == 0) 371 goto mapit; 372 373 #ifdef EXTENT_DEBUG 374 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr, 375 memaddr + memsize - 1); 376 #endif 377 error = extent_alloc_region(CHIP_MEM_EXTENT(v), memaddr, memsize, 378 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 379 if (error) { 380 #ifdef EXTENT_DEBUG 381 printf("mem: allocation failed (%d)\n", error); 382 extent_print(CHIP_MEM_EXTENT(v)); 383 #endif 384 return (error); 385 } 386 387 mapit: 388 *memhp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 389 390 return (0); 391 } 392 393 void 394 __C(CHIP,_mem_unmap)(v, memh, memsize, acct) 395 void *v; 396 bus_space_handle_t memh; 397 bus_size_t memsize; 398 int acct; 399 { 400 bus_addr_t memaddr; 401 int error; 402 403 if (acct == 0) 404 return; 405 406 #ifdef EXTENT_DEBUG 407 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize); 408 #endif 409 410 memaddr = memh - ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)); 411 412 #ifdef EXTENT_DEBUG 413 printf("mem: freeing 0x%lx to 0x%lx\n", memaddr, memaddr + memsize - 1); 414 #endif 415 416 error = extent_free(CHIP_MEM_EXTENT(v), memaddr, memsize, 417 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 418 if (error) { 419 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 420 __S(__C(CHIP,_mem_unmap)), memaddr, memaddr + memsize - 1, 421 error); 422 #ifdef EXTENT_DEBUG 423 extent_print(CHIP_MEM_EXTENT(v)); 424 #endif 425 } 426 } 427 428 int 429 __C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh) 430 void *v; 431 bus_space_handle_t memh, *nmemh; 432 bus_size_t offset, size; 433 { 434 435 *nmemh = memh + offset; 436 return (0); 437 } 438 439 int 440 __C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, flags, 441 addrp, bshp) 442 void *v; 443 bus_addr_t rstart, rend, *addrp; 444 bus_size_t size, align, boundary; 445 int flags; 446 bus_space_handle_t *bshp; 447 { 448 int prefetchable = flags & BUS_SPACE_MAP_PREFETCHABLE; 449 int linear = flags & BUS_SPACE_MAP_LINEAR; 450 bus_addr_t memaddr; 451 int error; 452 453 /* Requests for linear unprefetchable space can't be satisfied. */ 454 if (linear && !prefetchable) 455 return (EOPNOTSUPP); 456 457 /* 458 * Do the requested allocation. 459 */ 460 #ifdef EXTENT_DEBUG 461 printf("mem: allocating from 0x%lx to 0x%lx\n", rstart, rend); 462 #endif 463 error = extent_alloc_subregion(CHIP_MEM_EXTENT(v), rstart, rend, 464 size, align, boundary, 465 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 466 &memaddr); 467 if (error) { 468 #ifdef EXTENT_DEBUG 469 printf("mem: allocation failed (%d)\n", error); 470 extent_print(CHIP_MEM_EXTENT(v)); 471 #endif 472 } 473 474 #ifdef EXTENT_DEBUG 475 printf("mem: allocated 0x%lx to 0x%lx\n", memaddr, memaddr + size - 1); 476 #endif 477 478 *addrp = memaddr; 479 *bshp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 480 481 return (0); 482 } 483 484 void 485 __C(CHIP,_mem_free)(v, bsh, size) 486 void *v; 487 bus_space_handle_t bsh; 488 bus_size_t size; 489 { 490 491 /* Unmap does all we need to do. */ 492 __C(CHIP,_mem_unmap)(v, bsh, size, 1); 493 } 494 495 void * 496 __C(CHIP,_mem_vaddr)(v, bsh) 497 void *v; 498 bus_space_handle_t bsh; 499 { 500 /* 501 * We get linear access only with BUS_SPACE_MAP_PREFETCHABLE, 502 * so it should be OK if the caller doesn't use BWX instructions. 503 */ 504 return ((void *)bsh); 505 } 506 507 inline void 508 __C(CHIP,_mem_barrier)(v, h, o, l, f) 509 void *v; 510 bus_space_handle_t h; 511 bus_size_t o, l; 512 int f; 513 { 514 515 if ((f & BUS_SPACE_BARRIER_READ) != 0) 516 alpha_mb(); 517 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 518 alpha_wmb(); 519 } 520 521 inline u_int8_t 522 __C(CHIP,_mem_read_1)(v, memh, off) 523 void *v; 524 bus_space_handle_t memh; 525 bus_size_t off; 526 { 527 bus_addr_t addr; 528 529 addr = memh + off; 530 alpha_mb(); 531 return (alpha_ldbu((u_int8_t *)addr)); 532 } 533 534 inline u_int16_t 535 __C(CHIP,_mem_read_2)(v, memh, off) 536 void *v; 537 bus_space_handle_t memh; 538 bus_size_t off; 539 { 540 bus_addr_t addr; 541 542 addr = memh + off; 543 #ifdef DIAGNOSTIC 544 if (addr & 1) 545 panic(__S(__C(CHIP,_mem_read_2)) ": addr 0x%lx not aligned", 546 addr); 547 #endif 548 alpha_mb(); 549 return (alpha_ldwu((u_int16_t *)addr)); 550 } 551 552 inline u_int32_t 553 __C(CHIP,_mem_read_4)(v, memh, off) 554 void *v; 555 bus_space_handle_t memh; 556 bus_size_t off; 557 { 558 bus_addr_t addr; 559 560 addr = memh + off; 561 #ifdef DIAGNOSTIC 562 if (addr & 3) 563 panic(__S(__C(CHIP,_mem_read_4)) ": addr 0x%lx not aligned", 564 addr); 565 #endif 566 alpha_mb(); 567 return (*(u_int32_t *)addr); 568 } 569 570 inline u_int64_t 571 __C(CHIP,_mem_read_8)(v, memh, off) 572 void *v; 573 bus_space_handle_t memh; 574 bus_size_t off; 575 { 576 577 alpha_mb(); 578 579 /* XXX XXX XXX */ 580 panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); 581 } 582 583 #define CHIP_mem_read_multi_N(BYTES,TYPE) \ 584 void \ 585 __C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \ 586 void *v; \ 587 bus_space_handle_t h; \ 588 bus_size_t o, c; \ 589 TYPE *a; \ 590 { \ 591 \ 592 while (c-- > 0) { \ 593 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 594 BUS_SPACE_BARRIER_READ); \ 595 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 596 } \ 597 } 598 CHIP_mem_read_multi_N(1,u_int8_t) 599 CHIP_mem_read_multi_N(2,u_int16_t) 600 CHIP_mem_read_multi_N(4,u_int32_t) 601 CHIP_mem_read_multi_N(8,u_int64_t) 602 603 #define CHIP_mem_read_region_N(BYTES,TYPE) \ 604 void \ 605 __C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \ 606 void *v; \ 607 bus_space_handle_t h; \ 608 bus_size_t o, c; \ 609 TYPE *a; \ 610 { \ 611 \ 612 while (c-- > 0) { \ 613 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 614 o += sizeof *a; \ 615 } \ 616 } 617 CHIP_mem_read_region_N(1,u_int8_t) 618 CHIP_mem_read_region_N(2,u_int16_t) 619 CHIP_mem_read_region_N(4,u_int32_t) 620 CHIP_mem_read_region_N(8,u_int64_t) 621 622 inline void 623 __C(CHIP,_mem_write_1)(v, memh, off, val) 624 void *v; 625 bus_space_handle_t memh; 626 bus_size_t off; 627 u_int8_t val; 628 { 629 bus_addr_t addr; 630 631 addr = memh + off; 632 alpha_stb((u_int8_t *)addr, val); 633 alpha_mb(); 634 } 635 636 inline void 637 __C(CHIP,_mem_write_2)(v, memh, off, val) 638 void *v; 639 bus_space_handle_t memh; 640 bus_size_t off; 641 u_int16_t val; 642 { 643 bus_addr_t addr; 644 645 addr = memh + off; 646 #ifdef DIAGNOSTIC 647 if (addr & 1) 648 panic(__S(__C(CHIP,_mem_write_2)) ": addr 0x%lx not aligned", 649 addr); 650 #endif 651 alpha_stw((u_int16_t *)addr, val); 652 alpha_mb(); 653 } 654 655 inline void 656 __C(CHIP,_mem_write_4)(v, memh, off, val) 657 void *v; 658 bus_space_handle_t memh; 659 bus_size_t off; 660 u_int32_t val; 661 { 662 bus_addr_t addr; 663 664 addr = memh + off; 665 #ifdef DIAGNOSTIC 666 if (addr & 3) 667 panic(__S(__C(CHIP,_mem_write_4)) ": addr 0x%lx not aligned", 668 addr); 669 #endif 670 *(u_int32_t *)addr = val; 671 alpha_mb(); 672 } 673 674 inline void 675 __C(CHIP,_mem_write_8)(v, memh, off, val) 676 void *v; 677 bus_space_handle_t memh; 678 bus_size_t off; 679 u_int64_t val; 680 { 681 682 /* XXX XXX XXX */ 683 panic("%s not implemented", __S(__C(CHIP,_mem_write_8))); 684 alpha_mb(); 685 } 686 687 #define CHIP_mem_write_multi_N(BYTES,TYPE) \ 688 void \ 689 __C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \ 690 void *v; \ 691 bus_space_handle_t h; \ 692 bus_size_t o, c; \ 693 const TYPE *a; \ 694 { \ 695 \ 696 while (c-- > 0) { \ 697 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 698 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 699 BUS_SPACE_BARRIER_WRITE); \ 700 } \ 701 } 702 CHIP_mem_write_multi_N(1,u_int8_t) 703 CHIP_mem_write_multi_N(2,u_int16_t) 704 CHIP_mem_write_multi_N(4,u_int32_t) 705 CHIP_mem_write_multi_N(8,u_int64_t) 706 707 #define CHIP_mem_write_region_N(BYTES,TYPE) \ 708 void \ 709 __C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \ 710 void *v; \ 711 bus_space_handle_t h; \ 712 bus_size_t o, c; \ 713 const TYPE *a; \ 714 { \ 715 \ 716 while (c-- > 0) { \ 717 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 718 o += sizeof *a; \ 719 } \ 720 } 721 CHIP_mem_write_region_N(1,u_int8_t) 722 CHIP_mem_write_region_N(2,u_int16_t) 723 CHIP_mem_write_region_N(4,u_int32_t) 724 CHIP_mem_write_region_N(8,u_int64_t) 725 726 #define CHIP_mem_set_multi_N(BYTES,TYPE) \ 727 void \ 728 __C(__C(CHIP,_mem_set_multi_),BYTES)(v, h, o, val, c) \ 729 void *v; \ 730 bus_space_handle_t h; \ 731 bus_size_t o, c; \ 732 TYPE val; \ 733 { \ 734 \ 735 while (c-- > 0) { \ 736 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 737 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \ 738 BUS_SPACE_BARRIER_WRITE); \ 739 } \ 740 } 741 CHIP_mem_set_multi_N(1,u_int8_t) 742 CHIP_mem_set_multi_N(2,u_int16_t) 743 CHIP_mem_set_multi_N(4,u_int32_t) 744 CHIP_mem_set_multi_N(8,u_int64_t) 745 746 #define CHIP_mem_set_region_N(BYTES,TYPE) \ 747 void \ 748 __C(__C(CHIP,_mem_set_region_),BYTES)(v, h, o, val, c) \ 749 void *v; \ 750 bus_space_handle_t h; \ 751 bus_size_t o, c; \ 752 TYPE val; \ 753 { \ 754 \ 755 while (c-- > 0) { \ 756 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 757 o += sizeof val; \ 758 } \ 759 } 760 CHIP_mem_set_region_N(1,u_int8_t) 761 CHIP_mem_set_region_N(2,u_int16_t) 762 CHIP_mem_set_region_N(4,u_int32_t) 763 CHIP_mem_set_region_N(8,u_int64_t) 764 765 #define CHIP_mem_copy_region_N(BYTES) \ 766 void \ 767 __C(__C(CHIP,_mem_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 768 void *v; \ 769 bus_space_handle_t h1, h2; \ 770 bus_size_t o1, o2, c; \ 771 { \ 772 bus_size_t o; \ 773 \ 774 if ((h1 + o1) >= (h2 + o2)) { \ 775 /* src after dest: copy forward */ \ 776 for (o = 0; c != 0; c--, o += BYTES) { \ 777 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 778 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 779 } \ 780 } else { \ 781 /* dest after src: copy backwards */ \ 782 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) { \ 783 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 784 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 785 } \ 786 } \ 787 } 788 CHIP_mem_copy_region_N(1) 789 CHIP_mem_copy_region_N(2) 790 CHIP_mem_copy_region_N(4) 791 CHIP_mem_copy_region_N(8) 792
Indexes created Tue Oct 28 12:10:06 GMT 2025