pci_bwx_bus_mem_chipdep.c revision 1.14.4.1
1 /* $NetBSD: pci_bwx_bus_mem_chipdep.c,v 1.14.4.1 2001/09/13 01:12:56 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_MEM_BASE Mem space base to use. 74 * CHIP_MEM_EX_STORE 75 * If defined, device-provided static storage area 76 * for the memory space extent. If this is 77 * defined, CHIP_MEM_EX_STORE_SIZE must also be 78 * defined. If this is not defined, a static area 79 * will be declared. 80 * CHIP_MEM_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #include <machine/bwx.h> 88 89 #define __C(A,B) __CONCAT(A,B) 90 #define __S(S) __STRING(S) 91 92 /* mapping/unmapping */ 93 int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int, 94 bus_space_handle_t *, int)); 95 void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t, 96 bus_size_t, int)); 97 int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t, 98 bus_size_t, bus_size_t, bus_space_handle_t *)); 99 100 int __C(CHIP,_mem_translate) __P((void *, bus_addr_t, bus_size_t, 101 int, struct alpha_bus_space_translation *)); 102 int __C(CHIP,_mem_get_window) __P((void *, int, 103 struct alpha_bus_space_translation *)); 104 105 /* allocation/deallocation */ 106 int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t, 107 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 108 bus_space_handle_t *)); 109 void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t, 110 bus_size_t)); 111 112 /* get kernel virtual address */ 113 void * __C(CHIP,_mem_vaddr) __P((void *, bus_space_handle_t)); 114 115 /* mmap for user */ 116 paddr_t __C(CHIP,_mem_mmap) __P((void *, bus_addr_t, off_t, int, int)); 117 118 /* barrier */ 119 inline void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t, 120 bus_size_t, bus_size_t, int)); 121 122 /* read (single) */ 123 inline u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t, 124 bus_size_t)); 125 inline u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t, 126 bus_size_t)); 127 inline u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t, 128 bus_size_t)); 129 inline u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t, 130 bus_size_t)); 131 132 /* read multiple */ 133 void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t, 134 bus_size_t, u_int8_t *, bus_size_t)); 135 void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t, 136 bus_size_t, u_int16_t *, bus_size_t)); 137 void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t, 138 bus_size_t, u_int32_t *, bus_size_t)); 139 void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t, 140 bus_size_t, u_int64_t *, bus_size_t)); 141 142 /* read region */ 143 void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t, 144 bus_size_t, u_int8_t *, bus_size_t)); 145 void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t, 146 bus_size_t, u_int16_t *, bus_size_t)); 147 void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t, 148 bus_size_t, u_int32_t *, bus_size_t)); 149 void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t, 150 bus_size_t, u_int64_t *, bus_size_t)); 151 152 /* write (single) */ 153 inline void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t, 154 bus_size_t, u_int8_t)); 155 inline void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t, 156 bus_size_t, u_int16_t)); 157 inline void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t, 158 bus_size_t, u_int32_t)); 159 inline void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t, 160 bus_size_t, u_int64_t)); 161 162 /* write multiple */ 163 void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t, 164 bus_size_t, const u_int8_t *, bus_size_t)); 165 void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t, 166 bus_size_t, const u_int16_t *, bus_size_t)); 167 void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t, 168 bus_size_t, const u_int32_t *, bus_size_t)); 169 void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t, 170 bus_size_t, const u_int64_t *, bus_size_t)); 171 172 /* write region */ 173 void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t, 174 bus_size_t, const u_int8_t *, bus_size_t)); 175 void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t, 176 bus_size_t, const u_int16_t *, bus_size_t)); 177 void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t, 178 bus_size_t, const u_int32_t *, bus_size_t)); 179 void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t, 180 bus_size_t, const u_int64_t *, bus_size_t)); 181 182 /* set multiple */ 183 void __C(CHIP,_mem_set_multi_1) __P((void *, bus_space_handle_t, 184 bus_size_t, u_int8_t, bus_size_t)); 185 void __C(CHIP,_mem_set_multi_2) __P((void *, bus_space_handle_t, 186 bus_size_t, u_int16_t, bus_size_t)); 187 void __C(CHIP,_mem_set_multi_4) __P((void *, bus_space_handle_t, 188 bus_size_t, u_int32_t, bus_size_t)); 189 void __C(CHIP,_mem_set_multi_8) __P((void *, bus_space_handle_t, 190 bus_size_t, u_int64_t, bus_size_t)); 191 192 /* set region */ 193 void __C(CHIP,_mem_set_region_1) __P((void *, bus_space_handle_t, 194 bus_size_t, u_int8_t, bus_size_t)); 195 void __C(CHIP,_mem_set_region_2) __P((void *, bus_space_handle_t, 196 bus_size_t, u_int16_t, bus_size_t)); 197 void __C(CHIP,_mem_set_region_4) __P((void *, bus_space_handle_t, 198 bus_size_t, u_int32_t, bus_size_t)); 199 void __C(CHIP,_mem_set_region_8) __P((void *, bus_space_handle_t, 200 bus_size_t, u_int64_t, bus_size_t)); 201 202 /* copy */ 203 void __C(CHIP,_mem_copy_region_1) __P((void *, bus_space_handle_t, 204 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 205 void __C(CHIP,_mem_copy_region_2) __P((void *, bus_space_handle_t, 206 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 207 void __C(CHIP,_mem_copy_region_4) __P((void *, bus_space_handle_t, 208 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 209 void __C(CHIP,_mem_copy_region_8) __P((void *, bus_space_handle_t, 210 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 211 212 #ifndef CHIP_MEM_EX_STORE 213 static long 214 __C(CHIP,_mem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 215 #define CHIP_MEM_EX_STORE(v) (__C(CHIP,_mem_ex_storage)) 216 #define CHIP_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_mem_ex_storage)) 217 #endif 218 219 void 220 __C(CHIP,_bus_mem_init)(t, v) 221 bus_space_tag_t t; 222 void *v; 223 { 224 struct extent *ex; 225 226 /* 227 * Initialize the bus space tag. 228 */ 229 230 /* cookie */ 231 t->abs_cookie = v; 232 233 /* mapping/unmapping */ 234 t->abs_map = __C(CHIP,_mem_map); 235 t->abs_unmap = __C(CHIP,_mem_unmap); 236 t->abs_subregion = __C(CHIP,_mem_subregion); 237 238 t->abs_translate = __C(CHIP,_mem_translate); 239 t->abs_get_window = __C(CHIP,_mem_get_window); 240 241 /* allocation/deallocation */ 242 t->abs_alloc = __C(CHIP,_mem_alloc); 243 t->abs_free = __C(CHIP,_mem_free); 244 245 /* get kernel virtual address */ 246 t->abs_vaddr = __C(CHIP,_mem_vaddr); 247 248 /* mmap for user */ 249 t->abs_mmap = __C(CHIP,_mem_mmap); 250 251 /* barrier */ 252 t->abs_barrier = __C(CHIP,_mem_barrier); 253 254 /* read (single) */ 255 t->abs_r_1 = __C(CHIP,_mem_read_1); 256 t->abs_r_2 = __C(CHIP,_mem_read_2); 257 t->abs_r_4 = __C(CHIP,_mem_read_4); 258 t->abs_r_8 = __C(CHIP,_mem_read_8); 259 260 /* read multiple */ 261 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1); 262 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2); 263 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4); 264 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8); 265 266 /* read region */ 267 t->abs_rr_1 = __C(CHIP,_mem_read_region_1); 268 t->abs_rr_2 = __C(CHIP,_mem_read_region_2); 269 t->abs_rr_4 = __C(CHIP,_mem_read_region_4); 270 t->abs_rr_8 = __C(CHIP,_mem_read_region_8); 271 272 /* write (single) */ 273 t->abs_w_1 = __C(CHIP,_mem_write_1); 274 t->abs_w_2 = __C(CHIP,_mem_write_2); 275 t->abs_w_4 = __C(CHIP,_mem_write_4); 276 t->abs_w_8 = __C(CHIP,_mem_write_8); 277 278 /* write multiple */ 279 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1); 280 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2); 281 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4); 282 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8); 283 284 /* write region */ 285 t->abs_wr_1 = __C(CHIP,_mem_write_region_1); 286 t->abs_wr_2 = __C(CHIP,_mem_write_region_2); 287 t->abs_wr_4 = __C(CHIP,_mem_write_region_4); 288 t->abs_wr_8 = __C(CHIP,_mem_write_region_8); 289 290 /* set multiple */ 291 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1); 292 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2); 293 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4); 294 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8); 295 296 /* set region */ 297 t->abs_sr_1 = __C(CHIP,_mem_set_region_1); 298 t->abs_sr_2 = __C(CHIP,_mem_set_region_2); 299 t->abs_sr_4 = __C(CHIP,_mem_set_region_4); 300 t->abs_sr_8 = __C(CHIP,_mem_set_region_8); 301 302 /* copy */ 303 t->abs_c_1 = __C(CHIP,_mem_copy_region_1); 304 t->abs_c_2 = __C(CHIP,_mem_copy_region_2); 305 t->abs_c_4 = __C(CHIP,_mem_copy_region_4); 306 t->abs_c_8 = __C(CHIP,_mem_copy_region_8); 307 308 ex = extent_create(__S(__C(CHIP,_bus_mem)), 0x0UL, 0xffffffffUL, 309 M_DEVBUF, (caddr_t)CHIP_MEM_EX_STORE(v), CHIP_MEM_EX_STORE_SIZE(v), 310 EX_NOWAIT|EX_NOCOALESCE); 311 312 CHIP_MEM_EXTENT(v) = ex; 313 } 314 315 int 316 __C(CHIP,_mem_translate)(v, memaddr, memlen, flags, abst) 317 void *v; 318 bus_addr_t memaddr; 319 bus_size_t memlen; 320 int flags; 321 struct alpha_bus_space_translation *abst; 322 { 323 324 /* XXX */ 325 return (EOPNOTSUPP); 326 } 327 328 int 329 __C(CHIP,_mem_get_window)(v, window, abst) 330 void *v; 331 int window; 332 struct alpha_bus_space_translation *abst; 333 { 334 335 switch (window) { 336 case 0: 337 abst->abst_bus_start = 0; 338 abst->abst_bus_end = 0xffffffffUL; 339 abst->abst_sys_start = CHIP_MEM_SYS_START(v); 340 abst->abst_sys_end = CHIP_MEM_SYS_START(v) + abst->abst_bus_end; 341 abst->abst_addr_shift = 0; 342 abst->abst_size_shift = 0; 343 abst->abst_flags = ABST_DENSE|ABST_BWX; 344 break; 345 346 default: 347 panic(__S(__C(CHIP,_mem_get_window)) ": invalid window %d", 348 window); 349 } 350 351 return (0); 352 } 353 354 int 355 __C(CHIP,_mem_map)(v, memaddr, memsize, flags, memhp, acct) 356 void *v; 357 bus_addr_t memaddr; 358 bus_size_t memsize; 359 int flags; 360 bus_space_handle_t *memhp; 361 int acct; 362 { 363 int prefetchable = flags & BUS_SPACE_MAP_PREFETCHABLE; 364 int linear = flags & BUS_SPACE_MAP_LINEAR; 365 int error; 366 367 /* Requests for linear unprefetchable space can't be satisfied. */ 368 if (linear && !prefetchable) 369 return (EOPNOTSUPP); 370 371 if (acct == 0) 372 goto mapit; 373 374 #ifdef EXTENT_DEBUG 375 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr, 376 memaddr + memsize - 1); 377 #endif 378 error = extent_alloc_region(CHIP_MEM_EXTENT(v), memaddr, memsize, 379 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 380 if (error) { 381 #ifdef EXTENT_DEBUG 382 printf("mem: allocation failed (%d)\n", error); 383 extent_print(CHIP_MEM_EXTENT(v)); 384 #endif 385 return (error); 386 } 387 388 mapit: 389 *memhp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 390 391 return (0); 392 } 393 394 void 395 __C(CHIP,_mem_unmap)(v, memh, memsize, acct) 396 void *v; 397 bus_space_handle_t memh; 398 bus_size_t memsize; 399 int acct; 400 { 401 bus_addr_t memaddr; 402 int error; 403 404 if (acct == 0) 405 return; 406 407 #ifdef EXTENT_DEBUG 408 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize); 409 #endif 410 411 memaddr = memh - ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)); 412 413 #ifdef EXTENT_DEBUG 414 printf("mem: freeing 0x%lx to 0x%lx\n", memaddr, memaddr + memsize - 1); 415 #endif 416 417 error = extent_free(CHIP_MEM_EXTENT(v), memaddr, memsize, 418 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 419 if (error) { 420 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 421 __S(__C(CHIP,_mem_unmap)), memaddr, memaddr + memsize - 1, 422 error); 423 #ifdef EXTENT_DEBUG 424 extent_print(CHIP_MEM_EXTENT(v)); 425 #endif 426 } 427 } 428 429 int 430 __C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh) 431 void *v; 432 bus_space_handle_t memh, *nmemh; 433 bus_size_t offset, size; 434 { 435 436 *nmemh = memh + offset; 437 return (0); 438 } 439 440 int 441 __C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, flags, 442 addrp, bshp) 443 void *v; 444 bus_addr_t rstart, rend, *addrp; 445 bus_size_t size, align, boundary; 446 int flags; 447 bus_space_handle_t *bshp; 448 { 449 int prefetchable = flags & BUS_SPACE_MAP_PREFETCHABLE; 450 int linear = flags & BUS_SPACE_MAP_LINEAR; 451 bus_addr_t memaddr; 452 int error; 453 454 /* Requests for linear unprefetchable space can't be satisfied. */ 455 if (linear && !prefetchable) 456 return (EOPNOTSUPP); 457 458 /* 459 * Do the requested allocation. 460 */ 461 #ifdef EXTENT_DEBUG 462 printf("mem: allocating from 0x%lx to 0x%lx\n", rstart, rend); 463 #endif 464 error = extent_alloc_subregion(CHIP_MEM_EXTENT(v), rstart, rend, 465 size, align, boundary, 466 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 467 &memaddr); 468 if (error) { 469 #ifdef EXTENT_DEBUG 470 printf("mem: allocation failed (%d)\n", error); 471 extent_print(CHIP_MEM_EXTENT(v)); 472 #endif 473 } 474 475 #ifdef EXTENT_DEBUG 476 printf("mem: allocated 0x%lx to 0x%lx\n", memaddr, memaddr + size - 1); 477 #endif 478 479 *addrp = memaddr; 480 *bshp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 481 482 return (0); 483 } 484 485 void 486 __C(CHIP,_mem_free)(v, bsh, size) 487 void *v; 488 bus_space_handle_t bsh; 489 bus_size_t size; 490 { 491 492 /* Unmap does all we need to do. */ 493 __C(CHIP,_mem_unmap)(v, bsh, size, 1); 494 } 495 496 void * 497 __C(CHIP,_mem_vaddr)(v, bsh) 498 void *v; 499 bus_space_handle_t bsh; 500 { 501 /* 502 * We get linear access only with BUS_SPACE_MAP_PREFETCHABLE, 503 * so it should be OK if the caller doesn't use BWX instructions. 504 */ 505 return ((void *)bsh); 506 } 507 508 paddr_t 509 __C(CHIP,_mem_mmap)(v, addr, off, prot, flags) 510 void *v; 511 bus_addr_t addr; 512 off_t off; 513 int prot; 514 int flags; 515 { 516 517 return (alpha_btop(CHIP_MEM_SYS_START(v) + addr + off)); 518 } 519 520 inline void 521 __C(CHIP,_mem_barrier)(v, h, o, l, f) 522 void *v; 523 bus_space_handle_t h; 524 bus_size_t o, l; 525 int f; 526 { 527 528 if ((f & BUS_SPACE_BARRIER_READ) != 0) 529 alpha_mb(); 530 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 531 alpha_wmb(); 532 } 533 534 inline u_int8_t 535 __C(CHIP,_mem_read_1)(v, memh, off) 536 void *v; 537 bus_space_handle_t memh; 538 bus_size_t off; 539 { 540 bus_addr_t addr; 541 542 addr = memh + off; 543 alpha_mb(); 544 return (alpha_ldbu((u_int8_t *)addr)); 545 } 546 547 inline u_int16_t 548 __C(CHIP,_mem_read_2)(v, memh, off) 549 void *v; 550 bus_space_handle_t memh; 551 bus_size_t off; 552 { 553 bus_addr_t addr; 554 555 addr = memh + off; 556 #ifdef DIAGNOSTIC 557 if (addr & 1) 558 panic(__S(__C(CHIP,_mem_read_2)) ": addr 0x%lx not aligned", 559 addr); 560 #endif 561 alpha_mb(); 562 return (alpha_ldwu((u_int16_t *)addr)); 563 } 564 565 inline u_int32_t 566 __C(CHIP,_mem_read_4)(v, memh, off) 567 void *v; 568 bus_space_handle_t memh; 569 bus_size_t off; 570 { 571 bus_addr_t addr; 572 573 addr = memh + off; 574 #ifdef DIAGNOSTIC 575 if (addr & 3) 576 panic(__S(__C(CHIP,_mem_read_4)) ": addr 0x%lx not aligned", 577 addr); 578 #endif 579 alpha_mb(); 580 return (*(u_int32_t *)addr); 581 } 582 583 inline u_int64_t 584 __C(CHIP,_mem_read_8)(v, memh, off) 585 void *v; 586 bus_space_handle_t memh; 587 bus_size_t off; 588 { 589 590 alpha_mb(); 591 592 /* XXX XXX XXX */ 593 panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); 594 } 595 596 #define CHIP_mem_read_multi_N(BYTES,TYPE) \ 597 void \ 598 __C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \ 599 void *v; \ 600 bus_space_handle_t h; \ 601 bus_size_t o, c; \ 602 TYPE *a; \ 603 { \ 604 \ 605 while (c-- > 0) { \ 606 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 607 BUS_SPACE_BARRIER_READ); \ 608 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 609 } \ 610 } 611 CHIP_mem_read_multi_N(1,u_int8_t) 612 CHIP_mem_read_multi_N(2,u_int16_t) 613 CHIP_mem_read_multi_N(4,u_int32_t) 614 CHIP_mem_read_multi_N(8,u_int64_t) 615 616 #define CHIP_mem_read_region_N(BYTES,TYPE) \ 617 void \ 618 __C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \ 619 void *v; \ 620 bus_space_handle_t h; \ 621 bus_size_t o, c; \ 622 TYPE *a; \ 623 { \ 624 \ 625 while (c-- > 0) { \ 626 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 627 o += sizeof *a; \ 628 } \ 629 } 630 CHIP_mem_read_region_N(1,u_int8_t) 631 CHIP_mem_read_region_N(2,u_int16_t) 632 CHIP_mem_read_region_N(4,u_int32_t) 633 CHIP_mem_read_region_N(8,u_int64_t) 634 635 inline void 636 __C(CHIP,_mem_write_1)(v, memh, off, val) 637 void *v; 638 bus_space_handle_t memh; 639 bus_size_t off; 640 u_int8_t val; 641 { 642 bus_addr_t addr; 643 644 addr = memh + off; 645 alpha_stb((u_int8_t *)addr, val); 646 alpha_mb(); 647 } 648 649 inline void 650 __C(CHIP,_mem_write_2)(v, memh, off, val) 651 void *v; 652 bus_space_handle_t memh; 653 bus_size_t off; 654 u_int16_t val; 655 { 656 bus_addr_t addr; 657 658 addr = memh + off; 659 #ifdef DIAGNOSTIC 660 if (addr & 1) 661 panic(__S(__C(CHIP,_mem_write_2)) ": addr 0x%lx not aligned", 662 addr); 663 #endif 664 alpha_stw((u_int16_t *)addr, val); 665 alpha_mb(); 666 } 667 668 inline void 669 __C(CHIP,_mem_write_4)(v, memh, off, val) 670 void *v; 671 bus_space_handle_t memh; 672 bus_size_t off; 673 u_int32_t val; 674 { 675 bus_addr_t addr; 676 677 addr = memh + off; 678 #ifdef DIAGNOSTIC 679 if (addr & 3) 680 panic(__S(__C(CHIP,_mem_write_4)) ": addr 0x%lx not aligned", 681 addr); 682 #endif 683 *(u_int32_t *)addr = val; 684 alpha_mb(); 685 } 686 687 inline void 688 __C(CHIP,_mem_write_8)(v, memh, off, val) 689 void *v; 690 bus_space_handle_t memh; 691 bus_size_t off; 692 u_int64_t val; 693 { 694 695 /* XXX XXX XXX */ 696 panic("%s not implemented", __S(__C(CHIP,_mem_write_8))); 697 alpha_mb(); 698 } 699 700 #define CHIP_mem_write_multi_N(BYTES,TYPE) \ 701 void \ 702 __C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \ 703 void *v; \ 704 bus_space_handle_t h; \ 705 bus_size_t o, c; \ 706 const TYPE *a; \ 707 { \ 708 \ 709 while (c-- > 0) { \ 710 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 711 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 712 BUS_SPACE_BARRIER_WRITE); \ 713 } \ 714 } 715 CHIP_mem_write_multi_N(1,u_int8_t) 716 CHIP_mem_write_multi_N(2,u_int16_t) 717 CHIP_mem_write_multi_N(4,u_int32_t) 718 CHIP_mem_write_multi_N(8,u_int64_t) 719 720 #define CHIP_mem_write_region_N(BYTES,TYPE) \ 721 void \ 722 __C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \ 723 void *v; \ 724 bus_space_handle_t h; \ 725 bus_size_t o, c; \ 726 const TYPE *a; \ 727 { \ 728 \ 729 while (c-- > 0) { \ 730 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 731 o += sizeof *a; \ 732 } \ 733 } 734 CHIP_mem_write_region_N(1,u_int8_t) 735 CHIP_mem_write_region_N(2,u_int16_t) 736 CHIP_mem_write_region_N(4,u_int32_t) 737 CHIP_mem_write_region_N(8,u_int64_t) 738 739 #define CHIP_mem_set_multi_N(BYTES,TYPE) \ 740 void \ 741 __C(__C(CHIP,_mem_set_multi_),BYTES)(v, h, o, val, c) \ 742 void *v; \ 743 bus_space_handle_t h; \ 744 bus_size_t o, c; \ 745 TYPE val; \ 746 { \ 747 \ 748 while (c-- > 0) { \ 749 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 750 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \ 751 BUS_SPACE_BARRIER_WRITE); \ 752 } \ 753 } 754 CHIP_mem_set_multi_N(1,u_int8_t) 755 CHIP_mem_set_multi_N(2,u_int16_t) 756 CHIP_mem_set_multi_N(4,u_int32_t) 757 CHIP_mem_set_multi_N(8,u_int64_t) 758 759 #define CHIP_mem_set_region_N(BYTES,TYPE) \ 760 void \ 761 __C(__C(CHIP,_mem_set_region_),BYTES)(v, h, o, val, c) \ 762 void *v; \ 763 bus_space_handle_t h; \ 764 bus_size_t o, c; \ 765 TYPE val; \ 766 { \ 767 \ 768 while (c-- > 0) { \ 769 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 770 o += sizeof val; \ 771 } \ 772 } 773 CHIP_mem_set_region_N(1,u_int8_t) 774 CHIP_mem_set_region_N(2,u_int16_t) 775 CHIP_mem_set_region_N(4,u_int32_t) 776 CHIP_mem_set_region_N(8,u_int64_t) 777 778 #define CHIP_mem_copy_region_N(BYTES) \ 779 void \ 780 __C(__C(CHIP,_mem_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 781 void *v; \ 782 bus_space_handle_t h1, h2; \ 783 bus_size_t o1, o2, c; \ 784 { \ 785 bus_size_t o; \ 786 \ 787 if ((h1 + o1) >= (h2 + o2)) { \ 788 /* src after dest: copy forward */ \ 789 for (o = 0; c != 0; c--, o += BYTES) { \ 790 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 791 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 792 } \ 793 } else { \ 794 /* dest after src: copy backwards */ \ 795 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) { \ 796 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 797 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 798 } \ 799 } \ 800 } 801 CHIP_mem_copy_region_N(1) 802 CHIP_mem_copy_region_N(2) 803 CHIP_mem_copy_region_N(4) 804 CHIP_mem_copy_region_N(8) 805
Indexes created Tue Oct 28 12:10:06 GMT 2025